Datasheet

PIC16F87/88
DS30487D-page 132  2002-2013 Microchip Technology Inc.
15.2 Reset
The PIC16F87/88 differentiates between various kinds
of Reset:
• Power-on Reset (POR)
•MCLR
Reset during normal operation
•MCLR
Reset during Sleep
• WDT Reset during normal operation
• WDT wake-up during Sleep
• Brown-out Reset (BOR)
Some registers are not affected in any Reset condition.
Their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on Power-on Reset (POR), on the MCLR
and
WDT Reset, on MCLR
Reset during Sleep and Brown-
out Reset (BOR). They are not affected by a WDT
wake-up which is viewed as the resumption of normal
operation. The TO
and PD bits are set or cleared
differently in different Reset situations, as indicated in
Table 15-3. These bits are used in software to deter-
mine the nature of the Reset. Upon a POR, BOR or
wake-up from Sleep, the CPU requires approximately
5-10 s to become ready for code execution. This
delay runs in parallel with any other timers. See
Table 15-4 for a full description of Reset states of all
registers.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 15-1.
FIGURE 15-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
R
Q
External
Reset
MCLR
VDD
OSC1
WDT
Module
V
DD Rise
Detect
OST/PWRT
INTRC
WDT
Time-out
Power-on Reset
OST
10-bit Ripple Counter
PWRT
Chip_Reset
11-bit Ripple Counter
Reset
Enable OST
Enable PWRT
Sleep
Brown-out
Reset
BOREN
31.25 kHz