Datasheet

 2002-2013 Microchip Technology Inc. DS30487D-page 115
PIC16F87/88
REGISTER 12-3: ADCON1: A/D CONTROL REGISTER 1 (ADDRESS 9Fh) PIC16F88 DEVICES ONLY
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
ADFM ADCS2 VCFG1 VCFG0 — — — —
bit 7 bit 0
bit 7 ADFM: A/D Result Format Select bit
1 = Right justified. Six Most Significant bits of ADRESH are read as ‘0’.
0 = Left justified. Six Least Significant bits of ADRESL are read as ‘0’.
bit 6 ADCS2: A/D Clock Divide by 2 Select bit
1 = A/D clock source is divided by 2 when system clock is used
0 =Disabled
bit 5-4 VCFG<1:0>: A/D Voltage Reference Configuration bits
Note: The ANSEL bits for AN3 and AN2 inputs must be configured as analog inputs for the
V
REF+ and VREF- external pins to be used.
bit 3-0 Unimplemented: Read as ‘0’
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Logic State VREF+VREF-
00 AVDD AVSS
01 AVDD VREF-
10 VREF+ AVSS
11 VREF+ VREF-