Datasheet

PIC16F8X
DS30430B-page 46  1996 Microchip Technology Inc.
FIGURE 8-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME
FIGURE 8-13: TIME-OUT SEQUENCE ON POWER-UP (MCLR
TIED TO VDD): SLOW VDD RISE TIME
VDD
MCLR
INTERNAL POR
TPWRT
TOST
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
VDD
MCLR
V1
When VDD rises very slowly, it is possible that the TPWRT time-out and TOST time-out will expire before VDD
has reached its final value. In this example, the chip will reset properly if, and only if, V1 ≥ VDD min.
INTERNAL POR
TPWRT
TOST
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET