Datasheet

 1996 Microchip Technology Inc. DS30430B-page 21
PIC16F8X
5.0 I/O PORTS
The PIC16F8X has two ports, PORTA and PORTB.
Some port pins are multiplexed with an alternate func-
tion for other features on the device.
5.1 POR
TA and TRISA Registers
PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger
input and an open drain output. All other RA port pins
have TTL input levels and full CMOS output drivers. All
pins have data direction bits (TRIS registers) which can
configure these pins as output or input.
Setting a TRISA bit (=1) will make the corresponding
PORTA pin an input, i.e., put the corresponding output
driver in a hi-impedence mode. Clearing a TRISA bit
(=0) will make the corresponding PORTA pin an output,
i.e., put the contents of the output latch on the selected
pin.
Reading the PORTA register reads the status of the pins
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then this
value is modified and written to the port data latch.
The RA4 pin is multiplexed with the TMR0 clock input.
FIGURE 5-1: BLOCK DIAGRAM OF PINS
RA3:RA0
Note: I/O pins have protection diodes to VDD and VSS.
Data
bus
QD
Q
CK
QD
Q
CK
QD
EN
P
N
WR
Port
WR
TRIS
Data Latch
TRIS Latch
RD TRIS
RD PORT
TTL
input
buffer
VSS
VDD
I/O pin
EXAMPLE 5-1: INITIALIZING PORTA
CLRF PORTA ; Initialize PORTA by
; setting output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0x0F ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA<3:0> as inputs
; RA4 as outputs
; TRISA<7:5> are always
; read as '0'.
FIGURE 5-2: BLOCK DIAGRAM OF PIN RA4
Data
bus
WR
PORT
WR
TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
input
buffer
N
V
SS
RA4 pin
TMR0 clock input
Note: I/O pin has protection diodes to V
SS only.
QD
Q
CK
QD
Q
CK
EN
QD
EN
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