Datasheet

 1996 Microchip Technology Inc. DS30430B-page 103
PIC16F8X
APPENDIX A:FEATURE
IMPROVEMENTS
The following is the list of feature improvements over
the PIC16C5X microcontroller family:
1. Instruction word length is increased to 14 bits.
This allows larger page sizes both in program
memory (2K now as opposed to 512 before) and
the register file (128 bytes now versus 32 bytes
before).
2. A PC latch register (PCLATH) is added to han-
dle program memory paging. PA2, PA1 and PA0
bits are removed from the status register and
placed in the option register.
3. Data memory paging is redefined slightly. The
STATUS register is modified.
4. Four new instructions have been added:
RETURN , RETFIE , ADDLW , and SUBLW . Two
instructions, TRIS and OPTION, are being
phased out although they are kept for
compatibility with PIC16C5X.
5. OPTION and TRIS registers are made
addressable.
6. Interrupt capability is added. Interrupt vector is
at 0004h.
7. Stack size is increased to 8 deep.
8. Reset vector is changed to 0000h.
9. Reset of all registers is revisited. Five different
reset (and wake-up) types are recognized.
Registers are reset differently.
10. Wake up from SLEEP through interrupt is
added.
11. Two separate timers, the Oscillator Start-up
Timer (OST) and Power-up Timer (PWRT), are
included for more reliable power-up. These
timers are invoked selectively to avoid
unnecessary delays on power-up and wake-up.
12. PORTB has weak pull-ups and interrupt on
change features.
13. T0CKI pin is also a port pin (RA4/T0CKI).
14. FSR is a full 8-bit register.
15. "In system programming" is made possible. The
user can program PIC16FXX devices using only
five pins: V
DD
, V
SS
, V
PP
, RB6 (clock) and RB7
(data in/out).
APPENDIX B:COMPATIBILITY
To convert code written for PIC16C5X to PIC16F8X,
the user should take the following steps:
1. Remove any program memory page select
operations (PA2, PA1, PA0 bits) for CALL , GOTO .
2. Revisit any computed jump operations (write to
PC or add to PC, etc.) to make sure page bits
are set properly under the new scheme.
3. Eliminate any data memory page switching.
Redefine data variables for reallocation.
4. Verify all writes to STATUS, OPTION, and FSR
registers since these have changed.
5. Change reset vector to 0000h.
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