PIC16F8X 8-Bit CMOS Flash/EEPROM Microcontrollers Devices Included in this Data Sheet: • • • • • Pin Diagram PIC16F83 PIC16CR83 PIC16F84 PIC16CR84 Extended voltage range devices available (PIC16LF8X, PIC16LCR8X) PDIP, SOIC • Only 35 single word instructions to learn • All instructions single cycle (400 ns @ 10 MHz) except for program branches which are two-cycle • Operating speed: DC - 10 MHz clock input DC - 400 ns instruction cycle •1 18 RA1 RA3 2 17 RA0 RA4/T0CKI 3 16 OSC1/CLKIN MCLR 4
PIC16F8X Table of Contents 1.0 General Description ............................................................................................................................................ 3 2.0 PIC16F8X Device Varieties ................................................................................................................................ 5 3.0 Architectural Overview...................................................................................................................................
PIC16F8X 1.0 GENERAL DESCRIPTION The PIC16F8X is a group in the PIC16CXX family of low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers. This group contains the following devices: • • • • PIC16F83 PIC16CR83 PIC16F84 PIC16CR84 All PIC16/17 microcontrollers employ an advanced RISC architecture. PIC16CXX devices have enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources.
PIC16F8X PIC16F8X FAMILY OF DEVICES Clock Memory ) Hz (M o of er m p O ra a M y or F Fl as h um xim em M O PR EE — M RO 36 ta t by e yt P q re M Da 64 Da ta (b M pt M m ru er t In 4 e rc o Ti TMR0 es s) e( l du er ) ts ( RO P EE ) es s) g ro n ue M 13 l Vo ( g an u So e ns cy Features em io at Pi n Peripherals ry I/O TABLE 1-1: Vo g lta s R ge a ck Pa PIC16C84 10 — 1K PIC16F84(1) 2.0-6.
PIC16F8X 2.0 PIC16F8X DEVICE VARIETIES A variety of frequency ranges and packaging options are available. Depending on application and production requirements the proper device option can be selected using the information in this section. When placing orders, please use the “PIC16F8X Product Identification System” at the back of this data sheet to specify the correct part number. There are four device “types” as indicated in the device number. 1. 2. 3. 4. F, as in PIC16F84.
PIC16F8X NOTES: DS30430B-page 6 1996 Microchip Technology Inc.
PIC16F8X 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC16CXX family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16CXX uses a Harvard architecture. This architecture has the program and data accessed from separate memories. So the device has a program memory bus and a data memory bus.
PIC16F8X FIGURE 3-1: PIC16F8X BLOCK DIAGRAM 13 Flash/ROM Program Memory PIC16F83/CR83 512 x 14 PIC16F84/CR84 1K x 14 Data Bus 8 Program Counter 8 Level Stack (13-bit) Program Bus 14 EEPROM Data Memory RAM File Registers PIC16F83/R83/84 36 x 8 PIC16F84/CR84 68 x 8 7 EEDATA RAM Addr EEPROM Data Memory 64 x 8 EEADR Addr Mux Instruction reg 5 7 Direct Addr Indirect Addr TMR0 FSR reg RA4/T0CKI STATUS reg 8 MUX Power-up Timer Instruction Decode & Control Timing Generation Oscillator Start-up
PIC16F8X TABLE 3-1: PIC16F8X PINOUT DESCRIPTION DIP No. SOIC No. I/O/P Type OSC1/CLKIN 16 16 I OSC2/CLKOUT 15 15 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR 4 4 I/P ST Master clear (reset) input/programming voltage input. This pin is an active low reset to the device.
PIC16F8X Clocking Scheme/Instruction Cycle 3.1 3.2 The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2.
PIC16F8X MEMORY ORGANIZATION There are two memory blocks in the PIC16F8X. These are the program memory and the data memory. Each block has its own bus, so that access to each block can occur during the same oscillator cycle. The data memory can further be broken down into the general purpose RAM and the Special Function Registers (SFRs). The operation of the SFRs that control the “core” are described here.
PIC16F8X 4.2 Data Memory Organization 4.2.1 GENERAL PURPOSE REGISTER FILE The data memory is partitioned into two areas. The first is the Special Function Registers (SFR) area, while the second is the General Purpose Registers (GPR) area. The SFRs control the operation of the device. All devices have some amount of General Purpose Register (GPR) area. Each GPR is 8 bits wide and is accessed either directly or indirectly through the FSR (Section 4.5). Portions of data memory are banked.
PIC16F8X FIGURE 4-3: REGISTER FILE MAP PIC16F83/CR83 File Address FIGURE 4-4: REGISTER FILE MAP PIC16F84/CR84 File Address File Address 80h 00h Indirect addr.
PIC16F8X TABLE 4-1: Address REGISTER FILE SUMMARY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets (Note3) Bank 0 00h INDF Uses contents of FSR to address data memory (not a physical register) ---- ---- ---- ---- 01h TMR0 8-bit real-time clock/counter xxxx xxxx uuuu uuuu 02h PCL Low order 8 bits of the Program Counter (PC) 0000 0000 0000 0000 (2) TO PD Z DC 03h STATUS 04h FSR 05h PORTA — — — RA4/T0CKI RA3 RA2
PIC16F8X 4.2.2.1 STATUS REGISTER The STATUS register contains the arithmetic status of the ALU, the RESET status and the bank select bit for data memory. As with any register, the STATUS register can be the destination for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to device logic. Furthermore, the TO and PD bits are not writable.
PIC16F8X 4.2.2.2 OPTION REGISTER Note: The OPTION register is a readable and writable register which contains various control bits to configure the TMR0/WDT prescaler, the external INT interrupt, TMR0, and the weak pull-ups on PORTB. FIGURE 4-6: R/W-1 RBPU bit7 When the prescaler is assigned to the WDT (PSA = '1'), TMR0 has a 1:1 prescaler assignment.
PIC16F8X 4.2.2.3 INTCON REGISTER Note: The INTCON register is a readable and writable register which contains the various enable bits for all interrupt sources. FIGURE 4-7: R/W-0 GIE bit7 bit 7: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).
PIC16F8X 4.3 Program Counter: PCL and PCLATH The Program Counter (PC) is 13-bits wide. The low byte is the PCL register, which is a readable and writable register. The high byte of the PC (PC<12:8>) is not directly readable nor writable and comes from the PCLATH register. The PCLATH (PC latch high) register is a holding register for PC<12:8>. The contents of PCLATH are transferred to the upper byte of the program counter when the PC is loaded with a new value.
PIC16F8X 4.5 Indirect Addressing; INDF and FSR Registers EXAMPLE 4-2: The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing.
PIC16F8X NOTES: DS30430B-page 20 1996 Microchip Technology Inc.
PIC16F8X 5.0 I/O PORTS EXAMPLE 5-1: The PIC16F8X has two ports, PORTA and PORTB. Some port pins are multiplexed with an alternate function for other features on the device. 5.1 PORTA and TRISA Registers PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers. All pins have data direction bits (TRIS registers) which can configure these pins as output or input.
PIC16F8X TABLE 5-1: PORTA FUNCTIONS Name Bit0 Buffer Type RA0 RA1 RA2 RA3 RA4/T0CKI bit0 bit1 bit2 bit3 bit4 TTL TTL TTL TTL ST Function Input/output Input/output Input/output Input/output Input/output or external clock input for TMR0. Output is open drain type.
PIC16F8X PORTB and TRISB Registers 5.2 PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. A '1' on any bit in the TRISB register puts the corresponding output driver in a hi-impedance mode. A '0' on any bit in the TRISB register puts the contents of the output latch on the selected pin(s). Each of the PORTB pins have a weak internal pull-up. A single control bit can turn on all the pull-ups. This is done by clearing the RBPU (OPTION<7>) bit.
PIC16F8X EXAMPLE 5-2: INITIALIZING PORTB CLRF PORTB BSF MOVLW STATUS, RP0 0xCF MOVWF TRISB TABLE 5-3: Initialize PORTB by setting output data latches Select Bank 1 Value used to initialize data direction Set RB<3:0> as inputs RB<5:4> as outputs RB<7:6> as inputs PORTB FUNCTIONS Name RB0/INT ; ; ; ; ; ; ; ; ; ; Bit Buffer Type I/O Consistency Function (1) bit0 Input/output pin or external interrupt input. Internal software programmable weak pull-up. RB1 bit1 TTL Input/output pin.
PIC16F8X 5.3 I/O Programming Considerations 5.3.2 5.3.1 BI-DIRECTIONAL I/O PORTS The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5-5). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port.
PIC16F8X NOTES: DS30430B-page 26 1996 Microchip Technology Inc.
PIC16F8X 6.0 TIMER0 MODULE AND TMR0 REGISTER edge select bit, T0SE (OPTION<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.2. The Timer0 module timer/counter has the following features: • • • • • • The prescaler is shared between the Timer0 Module and the Watchdog Timer. The prescaler assignment is controlled, in software, by control bit PSA (OPTION<3>). Clearing bit PSA will assign the prescaler to the Timer0 Module.
PIC16F8X FIGURE 6-3: TMR0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 PC PC PC+1 MOVWF TMR0 Instruction Fetch PC+3 T0+1 T0 TMR0 PC+2 Instruction Execute PC+5 MOVF TMR0,W PC+6 MOVF TMR0,W NT0+1 NT0 Write TMR0 executed FIGURE 6-4: PC+4 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 + 1 TMR0 INTERRUPT T
PIC16F8X 6.2 Using TMR0 with External Clock 6.2.2 TMR0 INCREMENT DELAY When an external clock input is used for TMR0, it must meet certain requirements. The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the actual incrementing of the TMR0 register after synchronization.
PIC16F8X FIGURE 6-6: BLOCK DIAGRAM OF THE TMR0/WDT PRESCALER Data Bus CLKOUT (= Fosc/4) 0 RA4/T0CKI pin M U X 8 1 M U X 0 1 SYNC 2 Cycles TMR0 register T0SE T0CS 0 Watchdog Timer 1 M U X Set bit T0IF on overflow PSA 8-bit Prescaler 8 8 - to - 1MUX PS2:PS0 PSA WDT Enable bit 1 0 MUX PSA WDT time-out Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register. DS30430B-page 30 1996 Microchip Technology Inc.
PIC16F8X 6.3.1 SWITCHING PRESCALER ASSIGNMENT EXAMPLE 6-1: The prescaler assignment is fully under software control (i.e., it can be changed “on the fly” during program execution). Note: To avoid an unintended device RESET, the following instruction sequence (Example 6-1) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be taken even if the WDT is disabled. To change prescaler from the WDT to the Timer0 module use the sequence shown in Example 6-2.
PIC16F8X NOTES: DS30430B-page 32 1996 Microchip Technology Inc.
PIC16F8X 7.0 DATA EEPROM MEMORY The EEPROM data memory is readable and writable during normal operation (full VDD range). This memory is not directly mapped in the register file space. Instead it is indirectly addressed through the Special Function Registers. There are four SFRs used to read and write this memory. These registers are: • • • • EECON1 EECON2 EEDATA EEADR EEDATA holds the 8-bit data for read/write, and EEADR holds the address of the EEPROM location being accessed.
PIC16F8X EECON1 and EECON2 Registers EECON1 is the control register with five low order bits physically implemented. The upper-three bits are non-existent and read as '0's. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set, in software. They are cleared in hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation.
PIC16F8X 7.5 Write Verify 7.6 Depending on the application, good programming practice may dictate that the value written to the Data EEPROM should be verified (Example 7-3) to the desired value to be written. This should be used in applications where an EEPROM bit will be stressed near the specification limit. The Total Endurance disk will help determine your comfort level. There are conditions when the device may not want to write to the data EEPROM memory.
PIC16F8X NOTES: DS30430B-page 36 1996 Microchip Technology Inc.
PIC16F8X 8.0 SPECIAL FEATURES OF THE CPU What sets a microcontroller apart from other processors are special circuits to deal with the needs of real time applications. The PIC16F8X has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These features are: 8.
PIC16F8X FIGURE 8-1: R-u CP bit13 R-u CP CONFIGURATION WORD - PIC16CR83 AND PIC16CR84 R-u CP R-u CP R-u CP R-u CP R/P-u DP R-u CP R-u CP R-u CP R-u R-u R-u R-u PWRTE WDTE FOSC1 FOSC0 bit0 R = Readable bit P = Programmable bit - n = Value at POR reset u = unchanged bit 13:8 CP: Program Memory Code Protection bit 1 = Code protection off 0 = Program memory is code protected bit 7 DP: Data Memory Code Protection bit 1 = Code protection off 0 = Data memory is code protected bit 6:4 CP: Program Memo
PIC16F8X 8.2 Oscillator Configurations 8.2.1 OSCILLATOR TYPES TABLE 8-1: The PIC16F8X can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: • • • • LP XT HS RC Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor Ranges Tested: Mode Freq XT 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 10.0 MHz HS Note : 8.2.
PIC16F8X TABLE 8-2: PIC16F83/CR83/F84/CR84 CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Mode Freq OSC1/C1 OSC2/C2 LP 32 kHz 200 kHz 100 kHz 2 MHz 4 MHz 4 MHz 10 MHz 68 - 100 pF 15 - 33 pF 100 - 150 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 68 - 100 pF 15 - 33 pF 100 - 150 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF XT HS Note : Higher capacitance increases the stability of oscillator but also increases the start-up time. These values are for design guidance only.
PIC16F8X 8.2.4 RC OSCILLATOR For timing insensitive applications the RC device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (Rext) values, capacitor (Cext) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation.
PIC16F8X 8.3 Reset The PIC16F8X differentiates between various kinds of reset: • • • • • Power-on Reset (POR) MCLR reset during normal operation MCLR reset during SLEEP WDT Reset (during normal operation) WDT Wake-up (during SLEEP) Figure 8-8 shows a simplified block diagram of the on-chip reset circuit. The MCLR reset path has a noise filter to ignore small pulses. The electrical specifications state the pulse width requirements for the MCLR pin.
PIC16F8X TABLE 8-3: RESET CONDITION FOR PROGRAM COUNTER AND THE STATUS REGISTER Program Counter Condition Power-on Reset 000h STATUS Register 0001 1xxx MCLR Reset during normal operation 000h 000u uuuu MCLR Reset during SLEEP 000h 0001 0uuu WDT Reset (during normal operation) 000h 0000 1uuu WDT Wake-up PC + 1 Interrupt wake-up from SLEEP PC + 1 uuu0 0uuu (1) uuu1 0uuu Legend: u = unchanged, x = unknown.
PIC16F8X 8.4 Power-on Reset (POR) A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.2V - 1.7V). To take advantage of the POR, just tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A minimum rise time for VDD must be met for this to operate properly. See Electrical Specifications for details.
PIC16F8X FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 8-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET 1996 Microchip Technology Inc.
PIC16F8X FIGURE 8-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 8-13: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME V1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET When VDD rises very slowly, it is possible that the TPWRT time-out and TOST time-out will expire before VDD has reached its final value.
PIC16F8X 8.7 Time-out Sequence and Power-down Status Bits (TO/PD) On power-up (Figure 8-10, Figure 8-11, Figure 8-12 and Figure 8-13) the time-out sequence is as follows: First PWRT time-out is invoked after a POR has expired. Then the OST is activated. The total time-out will vary based on oscillator configuration and PWRTE configuration bit status. For example, in RC mode with the PWRT disabled, there will be no time-out at all.
PIC16F8X 8.9 Interrupts The PIC16F8X has 4 sources of interrupt: • • • • External interrupt RB0/INT pin TMR0 overflow interrupt PORTB change interrupts (pins RB7:RB4) Data EEPROM write complete interrupt The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also contains the individual and global interrupt enable bits. The global interrupt enable bit, GIE (INTCON<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts.
PIC16F8X FIGURE 8-17: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT 3 4 INT pin 1 1 INTF flag (INTCON<1>) Interrupt Latency 2 5 GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC Instruction fetched Inst (PC) Instruction executed Inst (PC-1) PC+1 Inst (PC+1) Inst (PC) 0004h PC+1 — Dummy Cycle 0005h Inst (0004h) Inst (0005h) Dummy Cycle Inst (0004h) Note 1: INTF flag is sampled here (every Q1).
PIC16F8X 8.10 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users wish to save key register values during an interrupt (e.g., W register and STATUS register). This is implemented in software. Example 8-1 stores and restores the STATUS and W register’s values. The User defined registers, W_TEMP and STATUS_TEMP are the temporary storage locations for the W and STATUS registers values.
PIC16F8X 8.11 Watchdog Timer (WDT) part (see DC specs). If longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT under software control by writing to the OPTION register. Thus, time-out periods up to 2.3 seconds can be realized. The Watchdog Timer is a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin.
PIC16F8X 8.12 Power-down Mode (SLEEP) 8.12.2 A device may be powered down (SLEEP) and later powered up (Wake-up from SLEEP). 8.12.1 SLEEP The Power-down mode is entered by executing the SLEEP instruction. If enabled, the Watchdog Timer is cleared (but keeps running), the PD bit (STATUS<3>) is cleared, the TO bit (STATUS<4>) is set, and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, low, or hi-impedance).
PIC16F8X 8.12.3 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO bit will not be set and PD bits will not be cleared.
PIC16F8X NOTES: DS30430B-page 54 1996 Microchip Technology Inc.
PIC16F8X 9.0 INSTRUCTION SET SUMMARY Each PIC16FXX instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16FXX instruction set summary in Table 9-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 9-1 shows the opcode field descriptions. Byte-oriented instructions: 'f' represents a file register designator and 'd' represents a destination designator.
PIC16F8X TABLE 9-2: INSTRUCTION SET SUMMARY Mnemonic, Operands ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF Description Cycles 14-Bit Opcode MSb f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate left f through carry Rotate right f through carr
PIC16F8X 9.1 Instruction Descriptions ANDLW AND Literal with W Syntax: [ label ] ANDLW 0 ≤ k ≤ 255 Operands: 0 ≤ k ≤ 255 (W) + k → (W) Operation: (W) .AND. (k) → (W) C, DC, Z Status Affected: Z ADDLW Add Literal and W Syntax: [ label ] ADDLW Operands: Operation: Status Affected: Encoding: 11 k 111x kkkk kkkk Encoding: 11 Description: The contents of the W register are added to the eight bit literal 'k' and the result is placed back in the W register.
PIC16F8X BCF Bit Clear f BTFSC Bit Test f, Skip if Clear Syntax: [ label ] BCF Syntax: [ label ] BTFSC f,b Operands: 0 ≤ f ≤ 127 0≤b≤7 Operands: 0 ≤ f ≤ 127 0≤b≤7 Operation: 0 → (f) Operation: skip if (f) = 0 Status Affected: None Status Affected: None Encoding: 01 f,b 00bb bfff ffff Description: Bit 'b' in register 'f' is cleared.
PIC16F8X BTFSS Bit Test f, skip if Set CLRF Clear f Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRF Operands: 0 ≤ f ≤ 127 0≤b<7 Operands: 0 ≤ f ≤ 127 Operation: 00h → (f) 1→Z Status Affected: Z Operation: skip if (f) = 1 Status Affected: None Encoding: Description: 01 11bb bfff ffff If bit 'b' in register 'f' is 1 then the next instruction is skipped.
PIC16F8X CLRWDT Clear Watchdog Timer DECF Decrement f Syntax: [ label ] CLRWDT Syntax: [ label ] DECF f,d Operands: None Operands: Operation: 00h → WDT 0 → WDT prescaler, 1 → TO 1 → PD 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) – 1 → (dest) Status Affected: Z Status Affected: Encoding: Description: Encoding: TO, PD 00 0000 0110 0100 The CLRWDT instruction resets the watchdog timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
PIC16F8X GOTO Go to address INCFSZ Increment f, Skip if 0 Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 2047 Operands: Operation: k → (PC<10:0>) (PCLATH<4:3>) → (PC<12:11>) 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) + 1 → (dest), skip if result = 0 None Status Affected: None Status Affected: Encoding: GOTO k 10 1kkk kkkk kkkk Description: GOTO is an unconditional branch. The eleven bit immediate value is loaded into PC bits <10:0>.
PIC16F8X IORWF Inclusive OR W with f MOVF Move f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) .OR. (f) → (W) Operation: (f) → (dest) Status Affected: Z Status Affected: Z Encoding: 00 IORWF f,d 0100 dfff ffff Description: Inclusive OR the W register to register 'f'. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'.
PIC16F8X NOP No Operation RETFIE Return from Interrupt Syntax: [ label ] Syntax: [ label ] Operands: None Operands: None Operation: No operation Operation: Status Affected: None TOS → (PC), 1 → GIE Status Affected: None Encoding: 00 NOP 0000 0xx0 0000 RETFIE No operation. Encoding: Words: 1 Description: Cycles: 1 The Stack is popped and Top of Stack (TOS) is loaded into the PC. Interrupts are enabled by setting the Global Interrupt Enable bit.
PIC16F8X RETURN Return from Subroutine RRF Rotate Right f through Carry Syntax: [ label ] Syntax: [ label ] Operands: None Operands: Operation: TOS → (PC) 0 ≤ f ≤ 127 d ∈ [0,1] Status Affected: None Operation: See description below Status Affected: C Encoding: Description: 00 0000 0000 1000 Return from subroutine. The stack is popped and the Top of Stack (TOS) is loaded into the program counter. This is a two cycle instruction.
PIC16F8X SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operands: Operation: k – (W) → (W) 0 ≤ f ≤ 127 d ∈ [0,1] Status Affected: C, DC, Z Operation: (f) – (W) → (dest) Status Affected: C, DC, Z Encoding: Description: SUBLW k 11 110x kkkk kkkk The W register is subtracted (2’s complement method) from the eight bit literal 'k'. The result is placed in the W register.
PIC16F8X SWAPF Swap f Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f<3:0>) → (dest<7:4>), (f<7:4>) → (dest<3:0>) Status Affected: 00 1 Cycles: 1 Example Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operation: (W) .XOR. k → (W) Status Affected: Z Description: 1110 dfff ffff The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0 the result is placed in W register. If 'd' is 1 the result is placed in register 'f'.
PIC16F8X 10.0 DEVELOPMENT SUPPORT 10.
PIC16F8X 10.6 PICDEM-1 Low-Cost PIC16/17 Demonstration Board The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchip’s microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs.
PIC16F8X MPASM allow full symbolic debugging from the Microchip Universal Emulator System (PICMASTER). Both versions include Microchip’s fuzzyLAB demonstration board for hands-on experience with fuzzy logic systems implementation. MPASM has the following features to assist in developing software for specific use applications. 10.14 • Provides translation of Assembler source code to object code for all Microchip microcontrollers. • Macro assembly capability.
DS30430B-page 70 SW006005 SW006005 SW006005 SW007002 SW007002 SW007002 SW007002 PIC16C61 PIC16C62, 62A, 64, 64A PIC16C620, 621, 622 SW006005 SW007002 SW007002 SW007002 SW007002 SW007002 SW007002 SW007002 SW007002 PIC16C71 PIC16C710, 711 PIC16C72 PIC16F83 PIC16C84 PIC16F84 PIC16C923, 924* SW006006 SW006006 SW006006 SW006006 SW006006 SW006006 SW006006 — SW006006 DV005001/ DV005002 DV005001/ DV005002 DV005001/ DV005002 DV005001/ DV005002 DV005001/ DV005002 DV005001/ DV005002 D
PIC16F8X Applicable Devices F83 CR83 F84 CR84 11.0 ELECTRICAL CHARACTERISTICS FOR PIC16F83 AND PIC16F84 Absolute Maximum Ratings † Ambient temperature under bias.............................................................................................................-55°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS .........................
PIC16F8X Applicable Devices F83 CR83 F84 CR84 TABLE 11-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) PIC16F84-04 PIC16F83-04 OSC RC XT HS LP PIC16F84-10 PIC16F83-10 VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: 4.0V to 6.0V 4.5 mA max. at 5.5V 14 µA max. at 4V WDT dis 4.0 MHz max. 4.0V to 6.0V 4.5 mA max. at 5.5V 14 µA max. at 4V WDT dis 4.0 MHz max. 4.
PIC16F8X Applicable Devices F83 CR83 F84 CR84 11.1 DC CHARACTERISTICS: DC Characteristics Power Supply Pins Parameter No.
PIC16F8X Applicable Devices F83 CR83 F84 CR84 11.2 DC CHARACTERISTICS: PIC16LF84, PIC16LF83 (Commercial, Industrial) DC Characteristics Power Supply Pins Parameter No. Sym Characteristic 2.0 1.5 * — — 6.0 — V V XT, RC, and LP osc configuration Device in SLEEP mode — VSS — V See section on Power-on Reset for details 0.05* — — D010 D010A — — 1 7.
PIC16F8X Applicable Devices F83 CR83 F84 CR84 11.3 DC CHARACTERISTICS: PIC16F84, PIC16F83 (Commercial, Industrial) PIC16LF84, PIC16LF83 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C ≤ TA ≤ +70°C (commercial) -40°C ≤ TA ≤ +85°C (industrial) Operating voltage VDD range as described in DC spec Section 11.1 and Section 11.2. DC Characteristics All Pins Except Power Supply Pins Parameter No.
PIC16F8X Applicable Devices F83 CR83 F84 CR84 11.4 DC CHARACTERISTICS: PIC16F84, PIC16F83 (Commercial, Industrial) PIC16LF84, PIC16F83 (Commercial, Industrial) DC Characteristics All Pins Except Power Supply Pins Parameter No.
PIC16F8X Applicable Devices F83 CR83 F84 CR84 TABLE 11-2: TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
PIC16F8X Applicable Devices F83 CR83 F84 CR84 11.5 Timing Diagrams and Specifications FIGURE 11-3: EXTERNAL CLOCK TIMING Q4 Q1 Q3 Q2 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 11-3: Parameter No. 1 EXTERNAL CLOCK TIMING REQUIREMENTS Sym Characteristic Min Typ† Max Units Conditions FOSC External CLKIN Frequency(1) DC DC DC DC — — — — 2 4 10 200 MHz MHz MHz kHz XT, RC osc XT, RC osc HS osc LP osc PIC16LF8X-04 PIC16F8X-04 PIC16F8X-10 PIC16LF8X-04 Oscillator Frequency(1) DC DC 0.1 0.1 1.
PIC16F8X Applicable Devices F83 CR83 F84 CR84 FIGURE 11-4: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 22 23 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: All tests must be done with specified capacitive loads (Figure 11-2) 50 pF on I/O pins and CLKOUT. TABLE 11-4: Parameter No.
PIC16F8X Applicable Devices F83 CR83 F84 CR84 FIGURE 11-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins TABLE 11-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS Parameter No.
PIC16F8X Applicable Devices F83 CR83 F84 CR84 FIGURE 11-6: TIMER0 CLOCK TIMINGS RA4/T0CKI 40 41 42 TABLE 11-6: Parameter No. 40 TIMER0 CLOCK REQUIREMENTS Sym Characteristic Tt0H T0CKI High Pulse Width Min No Prescaler With Prescaler 41 Tt0L T0CKI Low Pulse Width No Prescaler With Prescaler 42 * † Tt0P T0CKI Period Typ† Max Units Conditions 0.5TCY + 20 * — — ns 50 * 30 * — — — — ns ns 0.5TCY + 20 * — — ns 50 * 20 * — — — — ns ns 2.0V ≤ VDD ≤ 3.0V 3.0V ≤ VDD ≤ 6.
PIC16F8X Applicable Devices F83 CR83 F84 CR84 NOTES: DS30430B-page 82 1996 Microchip Technology Inc.
PIC16F8X Applicable Devices F83 CR83 F84 CR84 12.0 DC & AC CHARACTERISTICS GRAPHS/TABLES FOR PIC16F83 AND PIC16F84 NOT AVAILABLE AT THIS TIME. 1996 Microchip Technology Inc.
PIC16F8X Applicable Devices F83 CR83 F84 CR84 NOTES: DS30430B-page 84 1996 Microchip Technology Inc.
PIC16F8X Applicable Devices F83 CR83 F84 CR84 13.0 ELECTRICAL CHARACTERISTICS FOR PIC16CR83 AND PIC16CR84 Absolute Maximum Ratings † Ambient temperature under bias.............................................................................................................-55°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS .......................
PIC16F8X Applicable Devices F83 CR83 F84 CR84 TABLE 13-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) PIC16CR84-04 PIC16CR83-04 OSC RC XT HS LP PIC16CR84-10 PIC16CR83-10 VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: 4.0V to 6.0V 4.5 mA max. at 5.5V 14 µA max. at 4V WDT dis 4.0 MHz max. 4.0V to 6.0V 4.5 mA max. at 5.5V 14 µA max. at 4V WDT dis 4.
PIC16F8X Applicable Devices F83 CR83 F84 CR84 13.1 DC CHARACTERISTICS: DC Characteristics Power Supply Pins Parameter No.
PIC16F8X Applicable Devices F83 CR83 F84 CR84 13.2 DC CHARACTERISTICS: PIC16LCR84, PIC16LCR83 (Commercial, Industrial) DC Characteristics Power Supply Pins Parameter No. Sym Characteristic 2.0 1.5 * — — 6.0 — V V XT, RC, and LP osc configuration Device in SLEEP mode — VSS — V See section on Power-on Reset for details 0.05* — — D010 D010A — — 1 7.
PIC16F8X Applicable Devices F83 CR83 F84 CR84 13.3 DC CHARACTERISTICS: PIC16CR84A, PIC16CR83 (Commercial, Industrial) PIC16LCR84, PIC16LCR83 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C ≤ TA ≤ +70°C (commercial) -40°C ≤ TA ≤ +85°C (industrial) Operating voltage VDD range as described in DC spec Section 13.1 and Section 13.2. DC Characteristics All Pins Except Power Supply Pins Parameter No.
PIC16F8X Applicable Devices F83 CR83 F84 CR84 13.4 DC CHARACTERISTICS: PIC16CR84A, PIC16CR83 (Commercial, Industrial) PIC16LCR84A, PIC16LCR83 (Commercial, Industrial) DC Characteristics All Pins Except Power Supply Pins Parameter No.
PIC16F8X Applicable Devices F83 CR83 F84 CR84 TABLE 13-2: TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
PIC16F8X Applicable Devices F83 CR83 F84 CR84 13.5 Timing Diagrams and Specifications FIGURE 13-3: EXTERNAL CLOCK TIMING Q4 Q1 Q3 Q2 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 13-3: Parameter No. 1 EXTERNAL CLOCK TIMING REQUIREMENTS Sym Characteristic Min Typ† Max Units Conditions FOSC External CLKIN Frequency(1) DC DC DC DC — — — — 2 4 10 200 MHz MHz MHz kHz XT, RC osc XT, RC osc HS osc LP osc PIC16LCR8X-04 PIC16CR8X-04 PIC16CR8X-10 PIC16LCR8X-04 Oscillator Frequency(1) DC DC 0.1 0.
PIC16F8X Applicable Devices F83 CR83 F84 CR84 FIGURE 13-4: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 22 23 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: All tests must be done with specified capacitive loads (Figure 13-2) 50 pF on I/O pins and CLKOUT. TABLE 13-4: Parameter No.
PIC16F8X Applicable Devices F83 CR83 F84 CR84 FIGURE 13-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins TABLE 13-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS Parameter No.
PIC16F8X Applicable Devices F83 CR83 F84 CR84 FIGURE 13-6: TIMER0 CLOCK TIMINGS RA4/T0CKI 40 41 42 TABLE 13-6: Parameter No. 40 TIMER0 CLOCK REQUIREMENTS Sym Characteristic Tt0H T0CKI High Pulse Width Min No Prescaler With Prescaler 41 Tt0L T0CKI Low Pulse Width No Prescaler With Prescaler 42 * † Tt0P T0CKI Period Typ† Max Units Conditions 0.5TCY + 20 * — — ns 50 * 30 * — — — — ns ns 0.5TCY + 20 * — — ns 50 * 20 * — — — — ns ns 2.0V ≤ VDD ≤ 3.0V 3.0V ≤ VDD ≤ 6.
PIC16F8X Applicable Devices F83 CR83 F84 CR84 NOTES: DS30430B-page 96 1996 Microchip Technology Inc.
PIC16F8X 14.0 DC & AC CHARACTERISTICS GRAPHS/TABLES FOR PIC16CR83 AND PIC16CR84 NOT AVAILABLE AT THIS TIME. 1996 Microchip Technology Inc.
PIC16F8X Applicable Devices F83 CR83 F84 CR84 NOTES: DS30430B-page 98 1996 Microchip Technology Inc.
PIC16F8X 15.0 PACKAGING INFORMATION 15.1 Package Marking Information Example 18L PDIP MMMMMMMMMMMMXXX MMMMMMMMXXXXXXXX PIC16F84 10I/P 9305 CBA AABB CDE 18L SOIC Example MMMMMMMM XXXXXXXX AABB CDE PIC16LF84 04I/S0218 9310 CBA Legend: MM...M XX...X AA BB C Microchip part number information Customer specific information* Year code (last two digits of calendar year) Week code (week of January 1 is week ‘01’) Facility code of the plant at which wafer is manufactured C = Chandler, Arizona, U.S.A.
PIC16F8X 15.2 18-Lead Plastic Dual In-line (PDIP) - 300 mil N α C E1 E eA eB Pin No. 1 Indicator Area D S S1 Base Plane Seating Plane L B1 A1 A2 A e1 B D1 Package Group: Plastic Dual In-Line (PLA) Millimeters Symbol Min Max α 0° A A1 A2 B B1 C D D1 E E1 e1 eA eB L N S S1 – 0.381 3.048 0.355 1.524 0.203 22.479 20.320 7.620 6.096 2.489 7.620 7.874 3.048 18 0.889 0.127 DS30430B-page 100 Inches Notes Min Max 10° 0° 10° 4.064 – 3.810 0.559 1.524 0.381 23.495 20.320 8.255 7.112 2.
PIC16F8X 15.3 18-Lead Plastic Surface Mount (SOIC) - 300 mil e B h x 45° N Index Area E H α C Chamfer h x 45° L 1 2 3 D Seating Plane Base Plane CP A1 A Package Group: Plastic SOIC (SO) Millimeters Symbol Min Max Inches Notes Min Max α 0° 8° 0° 8° A A1 B C D E e H h L N CP 2.362 0.101 0.355 0.241 11.353 7.416 1.270 10.007 0.381 0.406 18 – 2.642 0.300 0.483 0.318 11.735 7.595 1.270 10.643 0.762 1.143 18 0.102 0.093 0.004 0.014 0.009 0.447 0.292 0.050 0.394 0.015 0.016 18 – 0.
PIC16F8X NOTES: DS30430B-page 102 1996 Microchip Technology Inc.
PIC16F8X APPENDIX A: FEATURE IMPROVEMENTS The following is the list of feature improvements over the PIC16C5X microcontroller family: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. Instruction word length is increased to 14 bits. This allows larger page sizes both in program memory (2K now as opposed to 512 before) and the register file (128 bytes now versus 32 bytes before). A PC latch register (PCLATH) is added to handle program memory paging.
PIC16F8X APPENDIX C: WHAT’S NEW Not applicable - new document. APPENDIX D: WHAT’S CHANGES Not applicable - new document. APPENDIX E: PIC16C84 TO PIC16F83/CR83 AND PIC16F84/CR84 CONVERSION CONSIDERATIONS This appendix discusses some of the issues that you may encounter as you convert your design from a PIC16C84 to a PIC16F83 or PIC16F84 device. These new devices are: • • • • PIC16F83 PIC16CR83 PIC16F84 PIC16CR84 Some of the issues that may be encountered are: 1. 2. 3. 4.
PIC14000 20 o em y or (x ) r wo 2 /I I SP C ,U T) R SA Peripherals g in m am 4K 192 s te by TMR0 I2C/ ADTMR SMBus M 14 11 22 2.7-6.
20 20 20 20 20 20 20 20 PIC16C54A PIC16CR54A PIC16C55 PIC16C56 PIC16C57 PIC16CR57B PIC16C58A PIC16CR58A im um qu — 2K — 2K 1K 512 — 512 RO en 2K — 2K — — — 512 — — — 73 73 72 72 25 24 25 25 25 25 RA D M M at a Fr e 512 yte s) em or TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 ) 12 12 20 20 12 20 12 12 12 12 ns 2.5-6.25 2.0-6.25 2.5-6.25 2.5-6.25 2.5-6.25 2.5-6.25 2.0-6.25 2.0-6.25 2.5-6.25 2.5-6.
1996 Microchip Technology Inc. 20 20 20 20 20 PIC16C556 PIC16C558 PIC16C620 PIC16C621 PIC16C622 2K 1K 512 2K 1K 512 128 80 80 128 80 80 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 H 2 2 2 — — — Yes Yes Yes — — — 3 4 4 4 3 3 13 13 13 13 13 13 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.
DS30430B-page 108 20 20 20 20 20 PIC16CR63(1) PIC16C64 PIC16C64A(1) PIC16CR64(1) PIC16C65 Features — 4K 4K — 2K 2K — 4K — 2K 2K 4K — — 2K — — 4K — 2K — — 192 TMR0, TMR1, TMR2 192 TMR0, TMR1, TMR2 192 TMR0, TMR1, TMR2 128 TMR0, TMR1, TMR2 128 TMR0, TMR1, TMR2 128 TMR0, TMR1, TMR2 192 TMR0, TMR1, TMR2 192 TMR0, TMR1, TMR2 128 TMR0, TMR1, TMR2 128 TMR0, TMR1, TMR2 128 TMR0, TMR1, TMR2 H 2 SPI/I2C, Yes USART 11 11 11 2 SPI/I2C, Yes USART 2 SPI/I2C, Yes USART 8 8 8
(M 14 rd wo Memory M e( ul od R SA T) Peripherals s) ls ne n ha Features 1996 Microchip Technology Inc.
10 10 10 10 PIC16F84(1) PIC16CR84(1) PIC16F83(1) PIC16CR83(1) F — 512 — 1K — — — — — 1K — 1K — — 512 EE (M 36 36 68 68 Da 64 64 64 64 ta Da em 64 ta y or P ( er T TMR0 TMR0 TMR0 TMR0 o M 4 4 4 4 4 Peripherals ) ts ol (V Features 13 13 13 13 13 2.0-6.0 18-pin DIP, SOIC 2.0-6.0 18-pin DIP, SOIC 2.0-6.0 18-pin DIP, SOIC 2.0-6.0 18-pin DIP, SOIC 2.0-6.
1996 Microchip Technology Inc. y or em M M T) R SA ) (s le u od ls ne n ha Features 4K 8 PIC16C924 176 TMR0, 1 SPI/I2C TMR1, TMR2 176 TMR0, 1 SPI/I2C TMR1, TMR2 am — — 5 — 4 Com 32 Seg 4 Com 32 Seg ,U 9 8 25 25 27 27 3.0-6.0 3.0-6.0 Yes Yes — — 64-pin SDIP(1), TQFP, 68-pin PLCC, DIE 64-pin SDIP(1), TQFP, 68-pin PLCC, DIE All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.
25 25 25 25 25 PIC17C42A PIC17CR42 PIC17C43 PIC17CR43 PIC17C44 im 8K — 4K — 2K u eq 4K — 2K — — RO EP O RO n 454 454 454 232 232 232 M of y en c M io at pe r Pr R y or em (M ) Hz og r am M Da AM Fr um 2K m em M ) ) TMR0,TMR1, 2 2 TMR2,TMR3 TMR0,TMR1, 2 2 TMR2,TMR3 TMR0,TMR1, 2 2 TMR2,TMR3 TMR0,TMR1, 2 2 TMR2,TMR3 TMR0,TMR1, 2 2 TMR2,TMR3 TMR0,TMR1, 2 2 TMR2,TMR3 ta ds (W or ( y or ) es by t er M Ti (s le od u er ia S Yes Yes Yes Yes Yes Yes C a
PIC16F8X PIN COMPATIBILITY Devices that have the same package type and VDD, VSS and MCLR pin locations are said to be pin compatible. This allows these different devices to operate in the same socket. Compatible devices may only requires minor software modification to allow proper operation in the application socket (ex., PIC16C56 and PIC16C61 devices). Not all devices in the same package size are pin compatible; for example, the PIC16C62 is compatible with the PIC16C63, but not the PIC16C55.
PIC16F8X NOTES: DS30430B-page 114 1996 Microchip Technology Inc.
PIC16F8X INDEX Interrupts .............................................................. 37, 48 A L Absolute Maximum Ratings ..........................................71, 85 ALU .......................................................................................7 Architectural Overview ..........................................................7 Assembler ...........................................................................68 Loading of PC........................................................
PIC16F8X Overflows .................................................................... 18 Underflows .................................................................. 18 STATUS ....................................................................7, 15, 43 T Time-out ..............................................................................43 Timer0 Switching Prescaler Assignment................................. 31 T0IF.............................................................................
PIC16F8X Figure 8-11: Time-out Sequence on Power-up (MCLR Not Tied To VDD): Case 2 ................ 45 Figure 8-12: Time-out Sequence on Power-up (MCLR Tied to VDD): Fast VDD Rise Time ..................................................... 46 Figure 8-13: Time-Out Sequence on Power-Up (MCLR Tied to VDD): Slow VDD Rise Time ..................................................... 46 Figure 8-14: Brown-out Protection Circuit 1...................... 47 Figure 8-15: Brown-out Protection Circuit 2...................
PIC16F8X NOTES: DS30430B-page 118 1996 Microchip Technology Inc.
PIC16F8X ON-LINE SUPPORT Microchip provides two methods of on-line support. These are the Microchip BBS and the Microchip World Wide Web (WWW) site. Use Microchip's Bulletin Board Service (BBS) to get current information and help about Microchip products. Microchip provides the BBS communication channel for you to use in extending your technical staff with microcontroller and memory experts.
PIC16F8X READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
PIC16F8X PIC16F8X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
WORLDWIDE SALES & SERVICE AMERICAS ASIA/PACIFIC EUROPE Corporate Office Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602 786-7200 Fax: 602 786-7277 Technical Support: 602 786-7627 Web: http://www.microchip.com Atlanta Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770 640-0034 Fax: 770 640-0307 Boston Microchip Technology Inc.
