Datasheet
2001-2013 Microchip Technology Inc. DS35007C-page 57
PIC16F84A
FIGURE 9-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
TABLE 9-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER REQUIREMENTS
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
30
31
34
I/O Pins
34
Parameter
No.
Sym Characteristic Min Typ† Max Units Conditions
30 TmcL MCLR
Pulse Width (low) 2 — — sVDD = 5.0V
31 T
WDT
Watchdog Timer Time-out
Period (No Prescaler)
71833msV
DD = 5.0V
32 T
OST
Oscillation Start-up Timer
Period
1024T
OSC ms TOSC = OSC1 period
33 T
PWRT Power-up Timer Period 28 72 132 ms VDD = 5.0V
34 T
IOZ
I/O hi-impedance from MCLR
Low or RESET
——100ns
† Data in "Typ" column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance
only and are not tested.