Datasheet

PIC16F84A
DS35007C-page 26  2001-2013 Microchip Technology Inc.
6.4 Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip when
V
DD rise is detected (in the range of 1.2V - 1.7V). To
take advantage of the POR, just tie the MCLR
pin
directly (or through a resistor) to V
DD. This will
eliminate external RC components usually needed to
create Power-on Reset. A minimum rise time for V
DD
must be met for this to operate properly. See Electrical
Specifications for details.
When the device starts normal operation (exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in RESET until the operating con-
ditions are met.
For additional information, refer to Application Note
AN607, "Power-up Trouble Shooting."
The POR circuit does not produce an internal RESET
when V
DD declines.
6.5 Power-up Timer (PWRT)
The Power-up Timer (PWRT) provides a fixed 72 ms
nominal time-out (T
PWRT) from POR (Figures 6-6
through 6-9). The Power-up Timer operates on an
internal RC oscillator. The chip is kept in RESET as
long as the PWRT is active. The PWRT delay allows
the V
DD to rise to an acceptable level (possible excep-
tion shown in Figure 6-9).
A configuration bit, PWRTE
, can enable/disable the
PWRT. See Register 6-1 for the operation of the
PWRTE bit for a particular device.
The power-up time delay T
PWRT will vary from chip to
chip due to V
DD, temperature, and process variation.
See DC parameters for details.
6.6 Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle delay (from OSC1 input) after the
PWRT delay ends (Figure 6-6, Figure 6-7, Figure 6-8
and Figure 6-9). This ensures the crystal oscillator or
resonator has started and stabilized.
The OST time-out (T
OST) is invoked only for XT, LP and
HS modes and only on Power-on Reset or wake-up
from SLEEP.
When V
DD rises very slowly, it is possible that the
T
PWRT time-out and TOST time-out will expire before
V
DD has reached its final value. In this case
(Figure 6-9), an external Power-on Reset circuit may
be necessary (Figure 6-5).
FIGURE 6-5: EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW V
DD POWER-UP)
Note 1: External Power-on Reset circuit is required
only if V
DD power-up rate is too slow. The
diode D helps discharge the capacitor
quickly when V
DD powers down.
2: R < 40 k is recommended to make sure
that voltage drop across R does not exceed
0.2V (max leakage current spec on MCLR
pin is 5 A). A larger voltage drop will
degrade V
IH level on the MCLR pin.
3: R1 = 100 to 1 k will limit any current flow-
ing into MCLR
from external capacitor C, in
the event of a MCLR
pin breakdown due to
ESD or EOS.
C
R1
R
D
V
DD
MCLR
PIC16FXX
VDD