PIC16F8X 18-pin Flash/EEPROM 8-Bit Microcontrollers Devices Included in this Data Sheet: Pin Diagrams PIC16F83 PIC16F84 PIC16CR83 PIC16CR84 Extended voltage range devices available (PIC16LF8X, PIC16LCR8X) PDIP, SOIC High Performance RISC CPU Features: • Only 35 single word instructions to learn • All instructions single cycle except for program branches which are two-cycle • Operating speed: DC - 10 MHz clock input DC - 400 ns instruction cycle Device Program Memory (words) Data Data RAM EEPROM (bytes
PIC16F8X Table of Contents 1.0 General Description ...................................................................................................................................................................... 3 2.0 PIC16F8X Device Varieties .......................................................................................................................................................... 5 3.0 Architectural Overview...............................................................................
PIC16F8X 1.0 GENERAL DESCRIPTION The PIC16F8X is a group in the PIC16CXX family of low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers. This group contains the following devices: • • • • PIC16F83 PIC16F84 PIC16CR83 PIC16CR84 All PIC® microcontrollers employ an advanced RISC architecture. PIC16F8X devices have enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources.
PIC16F8X TABLE 1-1 PIC16F8X FAMILY OF DEVICES PIC16F83 Clock Memory Maximum Frequency of Operation (MHz) PIC16CR83 10 PIC16F84 10 PIC16CR84 10 Flash Program Memory 512 — 1K — EEPROM Program Memory — — — — ROM Program Memory — 512 — 1K Data Memory (bytes) 36 36 68 68 Data EEPROM (bytes) 64 64 64 64 TMR0 TMR0 TMR0 TMR0 Interrupt Sources 4 4 4 4 I/O Pins 13 13 13 13 Voltage Range (Volts) 2.0-6.0 2.0-6.0 2.0-6.0 2.0-6.
PIC16F8X 2.0 PIC16F8X DEVICE VARIETIES A variety of frequency ranges and packaging options are available. Depending on application and production requirements the proper device option can be selected using the information in this section. When placing orders, please use the “PIC16F8X Product Identification System” at the back of this data sheet to specify the correct part number. There are four device “types” as indicated in the device number. 1. 2. 3. 4. F, as in PIC16F84.
PIC16F8X NOTES: DS30430D-page 6 1996-2013 Microchip Technology Inc.
PIC16F8X 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC16CXX family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16CXX uses a Harvard architecture. This architecture has the program and data accessed from separate memories. So the device has a program memory bus and a data memory bus.
PIC16F8X PIC16CXX devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register.
PIC16F8X TABLE 3-1 PIC16F8X PINOUT DESCRIPTION DIP No. SOIC No. I/O/P Type OSC1/CLKIN 16 16 I OSC2/CLKOUT 15 15 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR 4 4 I/P ST Master clear (reset) input/programming voltage input. This pin is an active low reset to the device.
PIC16F8X 3.1 Clocking Scheme/Instruction Cycle 3.2 The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2.
PIC16F8X MEMORY ORGANIZATION There are two memory blocks in the PIC16F8X. These are the program memory and the data memory. Each block has its own bus, so that access to each block can occur during the same oscillator cycle. The data memory can further be broken down into the general purpose RAM and the Special Function Registers (SFRs). The operation of the SFRs that control the “core” are described here.
PIC16F8X 4.2 Data Memory Organization 4.2.1 GENERAL PURPOSE REGISTER FILE The data memory is partitioned into two areas. The first is the Special Function Registers (SFR) area, while the second is the General Purpose Registers (GPR) area. The SFRs control the operation of the device. All devices have some amount of General Purpose Register (GPR) area. Each GPR is 8 bits wide and is accessed either directly or indirectly through the FSR (Section 4.5). Portions of data memory are banked.
PIC16F8X FIGURE 4-1: REGISTER FILE MAP PIC16F83/CR83 File Address FIGURE 4-2: REGISTER FILE MAP PIC16F84/CR84 File Address File Address 80h 00h Indirect addr.
PIC16F8X TABLE 4-1 Address REGISTER FILE SUMMARY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets (Note3) Bank 0 00h INDF Uses contents of FSR to address data memory (not a physical register) ---- ---- ---- ---- 01h TMR0 8-bit real-time clock/counter xxxx xxxx uuuu uuuu 02h PCL Low order 8 bits of the Program Counter (PC) 0000 0000 0000 0000 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu (2) TO 03h STATUS 04h FSR 05h PORT
PIC16F8X 4.2.2.1 STATUS REGISTER The STATUS register contains the arithmetic status of the ALU, the RESET status and the bank select bit for data memory. As with any register, the STATUS register can be the destination for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to device logic. Furthermore, the TO and PD bits are not writable.
PIC16F8X 4.2.2.2 OPTION_REG REGISTER Note: The OPTION_REG register is a readable and writable register which contains various control bits to configure the TMR0/WDT prescaler, the external INT interrupt, TMR0, and the weak pull-ups on PORTB. FIGURE 4-1: When the prescaler is assigned to the WDT (PSA = '1'), TMR0 has a 1:1 prescaler assignment.
PIC16F8X 4.2.2.3 INTCON REGISTER Note: The INTCON register is a readable and writable register which contains the various enable bits for all interrupt sources. FIGURE 4-1: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).
PIC16F8X 4.3 Program Counter: PCL and PCLATH The Program Counter (PC) is 13-bits wide. The low byte is the PCL register, which is a readable and writable register. The high byte of the PC (PC<12:8>) is not directly readable nor writable and comes from the PCLATH register. The PCLATH (PC latch high) register is a holding register for PC<12:8>. The contents of PCLATH are transferred to the upper byte of the program counter when the PC is loaded with a new value.
PIC16F8X 4.5 A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 4-2. Indirect Addressing; INDF and FSR Registers The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing.
PIC16F8X NOTES: DS30430D-page 20 1996-2013 Microchip Technology Inc.
PIC16F8X 5.0 I/O PORTS EXAMPLE 5-1: INITIALIZING PORTA CLRF PORTA BSF MOVLW STATUS, RP0 0x0F PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers. All pins have data direction bits (TRIS registers) which can configure these pins as output or input. MOVWF TRISA Setting a TRISA bit (=1) will make the corresponding PORTA pin an input, i.e.
PIC16F8X TABLE 5-1 PORTA FUNCTIONS Name Bit0 Buffer Type RA0 RA1 RA2 RA3 RA4/T0CKI bit0 bit1 bit2 bit3 bit4 TTL TTL TTL TTL ST Function Input/output Input/output Input/output Input/output Input/output or external clock input for TMR0. Output is open drain type.
PIC16F8X 5.2 PORTB and TRISB Registers PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. A '1' on any bit in the TRISB register puts the corresponding output driver in a hi-impedance mode. A '0' on any bit in the TRISB register puts the contents of the output latch on the selected pin(s). Each of the PORTB pins have a weak internal pull-up. A single control bit can turn on all the pull-ups. This is done by clearing the RBPU (OPTION_REG<7>) bit.
PIC16F8X EXAMPLE 5-1: INITIALIZING PORTB CLRF PORTB BSF MOVLW STATUS, RP0 0xCF MOVWF TRISB TABLE 5-3 Name RB0/INT ; ; ; ; ; ; ; ; ; ; Initialize PORTB by setting output data latches Select Bank 1 Value used to initialize data direction Set RB<3:0> as inputs RB<5:4> as outputs RB<7:6> as inputs PORTB FUNCTIONS Bit Buffer Type bit0 TTL/ST(1) I/O Consistency Function Input/output pin or external interrupt input. Internal software programmable weak pull-up. RB1 bit1 TTL Input/output pin.
PIC16F8X 5.3 I/O Programming Considerations 5.3.1 BI-DIRECTIONAL I/O PORTS 5.3.2 Any instruction which writes, operates internally as a read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, execute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs defined.
PIC16F8X NOTES: DS30430D-page 26 1996-2013 Microchip Technology Inc.
PIC16F8X 6.0 TIMER0 MODULE AND TMR0 REGISTER edge select bit, T0SE (OPTION_REG<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.2. The Timer0 module timer/counter has the following features: • • • • • • The prescaler is shared between the Timer0 Module and the Watchdog Timer. The prescaler assignment is controlled, in software, by control bit PSA (OPTION_REG<3>). Clearing bit PSA will assign the prescaler to the Timer0 Module.
PIC16F8X FIGURE 6-3: TMR0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 PC Instruction Fetch PC PC+1 MOVWF TMR0 MOVF TMR0,W PC+3 T0+1 T0 TMR0 PC+2 Instruction Execute PC+5 MOVF TMR0,W PC+6 MOVF TMR0,W NT0+1 NT0 Write TMR0 executed FIGURE 6-4: PC+4 MOVF TMR0,W MOVF TMR0,W Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 + 1 TMR0 INTERRUPT T
PIC16F8X 6.2 Using TMR0 with External Clock 6.2.2 TMR0 INCREMENT DELAY When an external clock input is used for TMR0, it must meet certain requirements. The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the actual incrementing of the TMR0 register after synchronization.
PIC16F8X FIGURE 6-5: TIMER0 TIMING WITH EXTERNAL CLOCK Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Ext. Clock Input or Prescaler Out (Note 2) (Note 3) Ext. Clock/Prescaler Output After Sampling Increment TMR0 (Q4) TMR0 T0 T0 + 1 T0 + 2 Note 1: Delay from clock input change to TMR0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on TMR0 input = 4Tosc max.
PIC16F8X 6.3.1 SWITCHING PRESCALER ASSIGNMENT EXAMPLE 6-1: The prescaler assignment is fully under software control (i.e., it can be changed “on the fly” during program execution). Note: To avoid an unintended device RESET, the following instruction sequence (Example 6-1) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be taken even if the WDT is disabled. To change prescaler from the WDT to the Timer0 module use the sequence shown in Example 6-2.
PIC16F8X NOTES: DS30430D-page 32 1996-2013 Microchip Technology Inc.
PIC16F8X 7.0 DATA EEPROM MEMORY The EEPROM data memory is readable and writable during normal operation (full VDD range). This memory is not directly mapped in the register file space. Instead it is indirectly addressed through the Special Function Registers. There are four SFRs used to read and write this memory. These registers are: • • • • EECON1 EECON2 EEDATA EEADR data memory is rated for high erase/write cycles. The write time is controlled by an on-chip timer.
PIC16F8X EECON1 and EECON2 Registers EECON1 is the control register with five low order bits physically implemented. The upper-three bits are nonexistent and read as '0's. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set, in software. They are cleared in hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation.
PIC16F8X 7.5 Write Verify SUBWF EEDATA, W BTFSS STATUS, Z GOTO WRITE_ERR : : Depending on the application, good programming practice may dictate that the value written to the Data EEPROM should be verified (Example 7-1) to the desired value to be written. This should be used in applications where an EEPROM bit will be stressed near the specification limit. The Total Endurance disk will help determine your comfort level. 7.
PIC16F8X NOTES: DS30430D-page 36 1996-2013 Microchip Technology Inc.
PIC16F8X 8.0 SPECIAL FEATURES OF THE CPU What sets a microcontroller apart from other processors are special circuits to deal with the needs of real time applications. The PIC16F8X has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection.
PIC16F8X 8.1 Configuration Bits The configuration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. These bits are mapped in program memory location 2007h. FIGURE 8-1: Address 2007h is beyond the user program memory space and it belongs to the special test/configuration memory space (2000h - 3FFFh). This space can only be accessed during programming.
PIC16F8X FIGURE 8-2: CONFIGURATION WORD - PIC16F83 AND PIC16F84 R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u CP CP CP CP CP CP CP CP R/P-u R/P-u CP CP R/P-u R/P-u R/P-u R/P-u PWRTE WDTE FOSC1 FOSC0 bit13 bit0 R = Readable bit P = Programmable bit - n = Value at POR reset u = unchanged bit 13:4 CP: Code Protection bit 1 = Code protection off 0 = All memory is code protected bit 3 PWRTE: Power-up Timer Enable bit 1 = Power-up timer is disabled 0 = Power-up timer is enabled bit 2 WDT
PIC16F8X FIGURE 8-4: EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION) OSC1 Clock from ext. system PIC16FXX Open TABLE 8-1 OSC2 CAPACITOR SELECTION FOR CERAMIC RESONATORS Ranges Tested: Mode Freq XT 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 10.0 MHz HS Note : OSC1/C1 OSC2/C2 47 - 100 pF 47 - 100 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF Recommended values of C1 and C2 are identical to the ranges tested table.
PIC16F8X FIGURE 8-6: EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT FIGURE 8-7: RC OSCILLATOR MODE VDD Rext 330 k 330 k 74AS04 74AS04 To Other Devices PIC16FXX Cext 74AS04 CLKIN Fosc/4 Recommended values: XTAL Note: RC OSCILLATOR For timing insensitive applications the RC device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (Rext) values, capacitor (Cext) values, and the operating temperature.
PIC16F8X FIGURE 8-8: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR WDT Module SLEEP WDT Time_Out Reset VDD rise detect Power_on_Reset S 10-bit Ripple counter R VDD OST/PWRT OST Chip_Reset Q OSC1/ CLKIN PWRT On-chip RC OSC(1) 10-bit Ripple counter Enable PWRT Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. DS30430D-page 42 See Table 8-5 Enable OST 1996-2013 Microchip Technology Inc.
PIC16F8X TABLE 8-3 RESET CONDITION FOR PROGRAM COUNTER AND THE STATUS REGISTER Program Counter Condition STATUS Register Power-on Reset 000h 0001 1xxx MCLR Reset during normal operation 000h 000u uuuu MCLR Reset during SLEEP 000h 0001 0uuu WDT Reset (during normal operation) 000h 0000 1uuu WDT Wake-up PC + 1 Interrupt wake-up from SLEEP PC + 1 uuu0 0uuu (1) uuu1 0uuu Legend: u = unchanged, x = unknown.
PIC16F8X 8.4 Power-on Reset (POR) A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.2V - 1.7V). To take advantage of the POR, just tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A minimum rise time for VDD must be met for this to operate properly. See Electrical Specifications for details.
PIC16F8X FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 8-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET 1996-2013 Microchip Technology Inc.
PIC16F8X FIGURE 8-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 8-13: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME V1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET When VDD rises very slowly, it is possible that the TPWRT time-out and TOST time-out will expire before VDD has reached its final value.
PIC16F8X 8.7 Time-out Sequence and Power-down Status Bits (TO/PD) On power-up (Figure 8-10, Figure 8-11, Figure 8-12 and Figure 8-13) the time-out sequence is as follows: First PWRT time-out is invoked after a POR has expired. Then the OST is activated. The total time-out will vary based on oscillator configuration and PWRTE configuration bit status. For example, in RC mode with the PWRT disabled, there will be no time-out at all.
PIC16F8X 8.9 Interrupts The PIC16F8X has 4 sources of interrupt: • • • • External interrupt RB0/INT pin TMR0 overflow interrupt PORTB change interrupts (pins RB7:RB4) Data EEPROM write complete interrupt The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also contains the individual and global interrupt enable bits. The global interrupt enable bit, GIE (INTCON<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts.
PIC16F8X FIGURE 8-17: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT 3 4 INT pin 1 1 INTF flag (INTCON<1>) Interrupt Latency 2 5 GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC Instruction fetched Inst (PC) Instruction executed Inst (PC-1) PC+1 Inst (PC+1) Inst (PC) 0004h PC+1 — Dummy Cycle 0005h Inst (0004h) Inst (0005h) Dummy Cycle Inst (0004h) Note 1: INTF flag is sampled here (every Q1).
PIC16F8X 8.10 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users wish to save key register values during an interrupt (e.g., W register and STATUS register). This is implemented in software. Example 8-1 stores and restores the STATUS and W register’s values. The User defined registers, W_TEMP and STATUS_TEMP are the temporary storage locations for the W and STATUS registers values.
PIC16F8X 8.11 Watchdog Timer (WDT) The Watchdog Timer is a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device has been stopped, for example, by execution of a SLEEP instruction. During normal operation a WDT time-out generates a device RESET.
PIC16F8X 8.12 Power-down Mode (SLEEP) 8.12.2 A device may be powered down (SLEEP) and later powered up (Wake-up from SLEEP). 8.12.1 SLEEP The Power-down mode is entered by executing the SLEEP instruction. If enabled, the Watchdog Timer is cleared (but keeps running), the PD bit (STATUS<3>) is cleared, the TO bit (STATUS<4>) is set, and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, low, or hi-impedance).
PIC16F8X 8.12.3 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO bit will not be set and PD bits will not be cleared.
PIC16F8X DS30430D-page 54 1996-2013 Microchip Technology Inc.
PIC16F8X 9.0 INSTRUCTION SET SUMMARY Each PIC16CXX instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16CXX instruction set summary in Table 9-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 9-1 shows the opcode field descriptions. For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator.
PIC16F8X TABLE 9-2 PIC16FXX INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f
PIC16F8X 9.1 Instruction Descriptions ADDLW Add Literal and W ANDLW AND Literal with W Syntax: [label] ADDLW Syntax: [label] ANDLW Operands: 0 k 255 Operands: 0 k 255 Operation: (W) + k (W) Operation: (W) .AND. (k) (W) Status Affected: C, DC, Z Status Affected: Z Encoding: 11 k 111x kkkk kkkk Encoding: 11 k 1001 kkkk kkkk Description: The contents of the W register are added to the eight bit literal 'k' and the result is placed in the W register.
PIC16F8X BCF Bit Clear f BTFSC Bit Test, Skip if Clear Syntax: [label] BCF Syntax: [label] BTFSC f,b Operands: 0 f 127 0b7 Operands: 0 f 127 0b7 Operation: 0 (f) Operation: skip if (f) = 0 Status Affected: None Status Affected: None Encoding: 01 f,b 00bb bfff ffff Description: Bit 'b' in register 'f' is cleared.
PIC16F8X BTFSS Bit Test f, Skip if Set CALL Call Subroutine Syntax: [label] BTFSS f,b Syntax: [ label ] CALL k Operands: 0 f 127 0b<7 Operands: 0 k 2047 Operation: (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> Status Affected: None Operation: skip if (f) = 1 Status Affected: None Encoding: Description: 01 1 Cycles: 1(2) If Skip: ffff Q1 Q2 Q3 Q4 Decode Read register 'f' Process data No-Operat ion (2nd Cycle) Q1 Q2 No-Operat ion Example bfff If bit 'b
PIC16F8X CLRF Clear f Syntax: [label] CLRF Operands: 0 f 127 Operation: 00h (f) 1Z Status Affected: Z Encoding: 00 f 0001 1fff ffff Description: The contents of register 'f' are cleared and the Z bit is set.
PIC16F8X COMF Complement f Syntax: [ label ] COMF Operands: 0 f 127 d [0,1] Operation: (f) (destination) Status Affected: Z Encoding: Description: 00 f,d 1001 dfff ffff The contents of register 'f' are complemented. If 'd' is 0 the result is stored in W. If 'd' is 1 the result is stored back in register 'f'.
PIC16F8X Unconditional Branch INCF Increment f Syntax: [ label ] Syntax: [ label ] Operands: 0 k 2047 Operands: Operation: k PC<10:0> PCLATH<4:3> PC<12:11> 0 f 127 d [0,1] Operation: (f) + 1 (destination) None Status Affected: Z GOTO Status Affected: Encoding: 10 GOTO k 1kkk kkkk kkkk dfff ffff 1 Words: 1 2 Cycles: 1 Words: Cycles: 2nd Cycle 1010 The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register.
PIC16F8X INCFSZ Increment f, Skip if 0 IORLW Inclusive OR Literal with W Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 k 255 Operation: (W) .OR.
PIC16F8X IORWF Inclusive OR W with f MOVLW Move Literal to W Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 k 255 Operation: k (W) Status Affected: None IORWF f,d Operation: (W) .OR. (f) (destination) Status Affected: Z Encoding: Description: 00 0100 dfff ffff Inclusive OR the W register with register 'f'. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'.
PIC16F8X NOP No Operation RETFIE Return from Interrupt Syntax: [ label ] Syntax: [ label ] Operands: None Operands: None Operation: No operation Operation: Status Affected: None TOS PC, 1 GIE Status Affected: None Encoding: 00 NOP 0000 Description: No operation. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Example 0xx0 0000 Encoding: Q2 Q3 0000 0000 1001 Description: Return from Interrupt. Stack is POPed and Top of Stack (TOS) is loaded in the PC.
PIC16F8X RETLW Return with Literal in W RETURN Return from Subroutine Syntax: [ label ] Syntax: [ label ] Operands: 0 k 255 Operands: None Operation: k (W); TOS PC Operation: TOS PC Status Affected: None Status Affected: None Encoding: Encoding: RETLW k 11 Description: 01xx kkkk kkkk The W register is loaded with the eight bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two cycle instruction.
PIC16F8X RLF Rotate Left f through Carry RRF Rotate Right f through Carry Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: See description below Operation: See description below Status Affected: C Status Affected: C Encoding: Description: RLF 00 1101 f,d dfff ffff The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0 the result is placed in the W register.
PIC16F8X SLEEP SUBLW Subtract W from Literal Syntax: [ label ] SUBLW k Syntax: [ label ] Operands: None Operands: 0 k 255 Operation: 00h WDT, 0 WDT prescaler, 1 TO, 0 PD Operation: k - (W) W) Status Affected: C, DC, Z SLEEP Encoding: 11 110x kkkk kkkk Description: The W register is subtracted (2’s complement method) from the eight bit literal 'k'. The result is placed in the W register. The power-down status bit, PD is cleared. Time-out status bit, TO is set.
PIC16F8X SUBWF Subtract W from f SWAPF Swap Nibbles in f Syntax: [ label ] Syntax: [ label ] SWAPF f,d Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - (W) destination) Operation: (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) Status Affected: None SUBWF f,d Status Affected: C, DC, Z Encoding: Description: 00 1 Cycles: 1 Example 1: dfff ffff Subtract (2’s complement method) W register from register 'f'.
PIC16F8X XORLW Exclusive OR Literal with W XORWF Exclusive OR W with f Syntax: [label] Syntax: [label] Operands: 0 k 255 Operands: Operation: (W) .XOR. k W) 0 f 127 d [0,1] Status Affected: Z Operation: (W) .XOR. (f) destination) Status Affected: Z Encoding: 11 XORLW k 1010 kkkk kkkk Description: The contents of the W register are XOR’ed with the eight bit literal 'k'. The result is placed in the W register.
PIC16F8X 10.0 DEVELOPMENT SUPPORT 10.
PIC16F8X 10.6 PICDEM-1 Low-Cost PIC MCU Demonstration Board The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchip’s microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs.
PIC16F8X MPASM has the following features to assist in developing software for specific use applications. • Provides translation of Assembler source code to object code for all Microchip microcontrollers. • Macro assembly capability. • Produces all the files (Object, Listing, Symbol, and special) required for symbolic debug with Microchip’s emulator systems. • Supports Hex (default), Decimal and Octal source and listing formats. MPASM provides a rich directive language to support programming of the PIC MCU.
Emulator Products Software Tools DS30430D-page 74 Programmers PRO MATE II Universal Programmer KEELOQ Evaluation Kit PICDEM-3 PICDEM-2 PICDEM-1 SEEVAL Designers Kit KEELOQ Programmer PICSTARTPlus Low-Cost Universal Dev.
PIC16F83/84 10.0 PIC16F8X ELECTRICAL CHARACTERISTICS FOR PIC16F83 AND PIC16F84 Absolute Maximum Ratings † Ambient temperature under bias.............................................................................................................-55C to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on VDD with respect to VSS ..................................................
PIC16F8X TABLE 10-1 PIC16F83/84 CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) PIC16F84-04 PIC16F83-04 OSC PIC16F84-10 PIC16F83-10 PIC16LF84-04 PIC16LF83-04 RC VDD: IDD: IPD: Freq: 4.0V to 6.0V 4.5 mA max. at 5.5V 14 A max. at 4V WDT dis 4.0 MHz max. VDD: IDD: IPD: Freq: 4.5V to 5.5V 1.8 mA typ. at 5.5V 1.0 A typ. at 5.5V WDT dis 4..0 MHz max. VDD: IDD: IPD: Freq: 2.0V to 6.0V 4.5 mA max. at 5.5V 7.0 A max. at 2V WDT dis 2.
PIC16F83/84 10.1 DC CHARACTERISTICS: DC Characteristics Power Supply Pins Parameter No.
PIC16F8X 10.2 DC CHARACTERISTICS: PIC16F83/84 PIC16LF84, PIC16LF83 (Commercial, Industrial) DC Characteristics Power Supply Pins Parameter No.
PIC16F8X PIC16F83/84 10.3 DC CHARACTERISTICS: PIC16F84, PIC16F83 (Commercial, Industrial) PIC16LF84, PIC16LF83 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) Operating voltage VDD range as described in DC spec Section 10.1 and Section 10.2. DC Characteristics All Pins Except Power Supply Pins Parameter No.
PIC16F8X 10.4 PIC16F83/84 DC CHARACTERISTICS: PIC16F84, PIC16F83 (Commercial, Industrial) PIC16LF84, PIC16F83 (Commercial, Industrial) DC Characteristics All Pins Except Power Supply Pins Sym Characteristic D100 COSC2 Capacitive Loading Specs on Output Pins OSC2 pin D101 CIO Parameter No.
PIC16F8X PIC16F83/84 TABLE 10-2 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
PIC16F8X 10.5 PIC16F83/84 Timing Diagrams and Specifications FIGURE 10-3: EXTERNAL CLOCK TIMING Q4 Q1 Q3 Q2 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 10-3 Parameter No. EXTERNAL CLOCK TIMING REQUIREMENTS Sym FOSC 1 Tosc Characteristic Min Typ† Max Units External CLKIN Frequency(1) DC DC DC DC — — — — 2 4 10 200 MHz MHz MHz kHz XT, RC osc XT, RC osc HS osc LP osc PIC16LF8X-04 PIC16F8X-04 PIC16F8X-10 PIC16LF8X-04 Oscillator Frequency(1) DC DC 0.1 0.1 1.
PIC16F8X PIC16F83/84 FIGURE 10-4: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 22 23 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: All tests must be done with specified capacitive loads (Figure 10-2) 50 pF on I/O pins and CLKOUT. TABLE 10-4 Parameter No.
PIC16F8X PIC16F83/84 FIGURE 10-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins TABLE 10-5 RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS Parameter No.
PIC16F8X PIC16F83/84 FIGURE 10-6: TIMER0 CLOCK TIMINGS RA4/T0CKI 40 41 42 TABLE 10-6 Parameter No. 40 TIMER0 CLOCK REQUIREMENTS Sym Characteristic Tt0H T0CKI High Pulse Width No Prescaler With Prescaler 41 Tt0L T0CKI Low Pulse Width No Prescaler With Prescaler 42 * † Tt0P T0CKI Period Min Typ† Max Units 0.5TCY + 20 * — — ns 50 * 30 * — — — — ns ns Conditions 2.0V VDD 3.0V 3.0V VDD 6.0V 0.5TCY + 20 * — — ns 50 * 20 * — — — — ns ns 2.0V VDD 3.0V 3.0V VDD 6.
PIC16F8X PIC16F83/84 NOTES: DS30430D-page 11-86 1996-2013 Microchip Technology Inc.
PIC16CR83/84 11.0 PIC16F8X ELECTRICAL CHARACTERISTICS FOR PIC16CR83 AND PIC16CR84 Absolute Maximum Ratings † Ambient temperature under bias.............................................................................................................-55C to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on VDD with respect to VSS ...............................................
PIC16F8X TABLE 11-1 PIC16CR83/84 CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) PIC16CR84-04 PIC16CR83-04 OSC PIC16CR84-10 PIC16CR83-10 PIC16LCR84-04 PIC16LCR83-04 RC VDD: IDD: IPD: Freq: 4.0V to 6.0V 4.5 mA max. at 5.5V 14 A max. at 4V WDT dis 4.0 MHz max. VDD: IDD: IPD: Freq: 4.5V to 5.5V 1.8 mA typ. at 5.5V 1.0 A typ. at 5.5V WDT dis 4..0 MHz max. VDD: IDD: IPD: Freq: 2.0V to 6.0V 4.5 mA max. at 5.5V 5 A max. at 2V WDT dis 2.
PIC16CR83/84 11.1 DC CHARACTERISTICS: DC Characteristics Power Supply Pins Parameter No.
PIC16F8X 11.2 PIC16CR83/84 DC CHARACTERISTICS: PIC16LCR84, PIC16LCR83 (Commercial, Industrial) DC Characteristics Power Supply Pins Parameter No.
PIC16F8X PIC16CR83/84 11.3 DC CHARACTERISTICS: PIC16CR84, PIC16CR83 (Commercial, Industrial) PIC16LCR84, PIC16LCR83 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) Operating voltage VDD range as described in DC spec Section 11.1 and Section 11.2. DC Characteristics All Pins Except Power Supply Pins Parameter No. Sym Characteristic Min Typ† Max Units Conditions VSS — 0.8 V 4.
PIC16F8X 11.4 PIC16CR83/84 DC CHARACTERISTICS: PIC16CR84, PIC16CR83 (Commercial, Industrial) PIC16LCR84, PIC16LCR83 (Commercial, Industrial) DC Characteristics All Pins Except Power Supply Pins Sym Characteristic D100 COSC2 Capacitive Loading Specs on Output Pins OSC2 pin D101 CIO D120 D121 ED VDRW Parameter No.
PIC16F8X PIC16CR83/84 TABLE 11-2 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
PIC16F8X 11.5 PIC16CR83/84 Timing Diagrams and Specifications FIGURE 11-3: EXTERNAL CLOCK TIMING Q4 Q1 Q3 Q2 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 11-3 Parameter No.
PIC16F8X PIC16CR83/84 FIGURE 11-4: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 22 23 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: All tests must be done with specified capacitive loads (Figure 11-2) 50 pF on I/O pins and CLKOUT. TABLE 11-4 Parameter No.
PIC16F8X PIC16CR83/84 FIGURE 11-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins TABLE 11-5 Parameter No.
PIC16F8X PIC16CR83/84 FIGURE 11-6: TIMER0 CLOCK TIMINGS RA4/T0CKI 40 41 42 TABLE 11-6 Parameter No. 40 TIMER0 CLOCK REQUIREMENTS Sym Tt0H Characteristic T0CKI High Pulse Width Min No Prescaler With Prescaler 41 Tt0L T0CKI Low Pulse Width No Prescaler With Prescaler 42 * † Tt0P T0CKI Period Typ† Max Units 0.5TCY + 20 * — — ns 50 * 30 * — — — — ns ns Conditions 2.0V VDD 3.0V 3.0V VDD 6.0V 0.5TCY + 20 * — — ns 50 * 20 * — — — — ns ns 2.0V VDD 3.0V 3.
PIC16F8X PIC16CR83/84 NOTES: DS30430D-page 11-98 1996-2013 Microchip Technology Inc.
PIC16F8X 12.0 DC & AC CHARACTERISTICS GRAPHS/TABLES The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range.
PIC16F8X FIGURE 12-2: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 20 PF Measured on DIP Packages, T = 25°C 5.5 5.0 R = 5k 4.5 4.0 Fosc (MHz) 3.5 R = 10k 3.0 2.5 2.0 1.5 1.0 R = 100k 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) DS30430D-page 11-100 1996-2013 Microchip Technology Inc.
PIC16F8X FIGURE 12-3: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 100 PF Measured on DIP Packages, T = 25°C 1.8 R = 5k 1.6 1.4 Fosc (MHz) 1.2 1.0 R = 10k 0.8 0.6 0.4 0.2 R = 100k 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) FIGURE 12-4: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 300 PF Measured on DIP Packages, T = 25°C 0.6 R = 5k FOSC (MHz) 0.5 0.4 R = 10k 0.3 0.2 0.1 R = 100k 0.0 1996-2013 Microchip Technology Inc. 2.0 2.5 3.0 3.5 4.0 4.5 VDD (Volts) 5.
PIC16F8X FIGURE 12-5: TYPICAL IPD vs. VDD, WATCHDOG DISABLED FIGURE 12-6: TYPICAL IPD vs. VDD, WATCHDOG ENABLED 6.0 10 9 5.0 8 T = 25C T = 25C 7 6 IPD (A) IPD (A) 4.0 3.0 5 4 3 2 2.0 1 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.0 VDD (Volts) 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) FIGURE 12-7: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS vs. VDD 1.40 VTH (Volts) 1.30 1.20 ( Typ 1.10 +25 C) 1.00 0.90 0.80 0.70 2.0 2.5 3.0 3.5 4.0 VDD (Volts) 4.5 5.0 5.5 6.
PIC16F8X FIGURE 12-8: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN XT, HS, AND LP MODES) vs. VDD 3.0 2.8 2.6 VTH (Volts) 2.4 2.2 2.0 C) (+25 Typ 1.8 1.6 1.4 1.2 1.0 0.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 5.5 6.0 VDD (Volts) Note: This input pin is CMOS input. FIGURE 12-9: VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) vs. VDD 5.0 4.5 4.0 VIH, VIL (Volts) 3.5 3.0 V IH 25C ty p + 2.5 2.0 1.5 VIL typ +25C 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 VDD (Volts) 4.5 5.
PIC16F8X FIGURE 12-10: TYPICAL IDD vs. FREQUENCY (RC MODE @20PF, 25C) TYPICAL IDD vs FREQ (RC MODE @20pF) 10000 1000 6.0V 5.5V 100 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V 10 100000 1000000 10000000 FREQ (Hz) DS30430D-page 11-104 1996-2013 Microchip Technology Inc.
PIC16F8X FIGURE 12-11: TYPICAL IDD vs. FREQUENCY (RC MODE @100PF, 25C) TYPICAL IDD vs FREQ (RC MODE @100 pF) 10000 1000 6.0V 5.5V 100 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V 10 10000 100000 1000000 10000000 FREQ (Hz) 1996-2013 Microchip Technology Inc.
PIC16F8X FIGURE 12-12: TYPICAL IDD vs. FREQUENCY (RC MODE @300PF, 25C) TYPICAL IDD vs FREQ (RC MODE @300pF) 1000 6.0V 5.5V 100 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V 10 10000 100000 1000000 FREQ (Hz) DS30430D-page 11-106 1996-2013 Microchip Technology Inc.
PIC16F8X FIGURE 12-14: TRANSCONDUCTANCE (gm) OF HS OSCILLATOR vs. VDD 50 9000 45 8000 40 7000 35 6000 30 5000 gm (A/V) WDT period (ms) FIGURE 12-13: WDT TIMER TIME-OUT PERIOD vs. VDD Typ +25C 25 Typ +25C 4000 20 3000 15 2000 10 100 5 2.0 3.0 4.0 VDD (Volts) 1996-2013 Microchip Technology Inc. 5.0 6.0 0 2.0 3.0 4.0 5.0 VDD (Volts) 6.
PIC16F8X FIGURE 12-15: TRANSCONDUCTANCE (gm) OF LP OSCILLATOR vs. VDD FIGURE 12-16: TRANSCONDUCTANCE (gm) OF XT OSCILLATOR vs. VDD 2500 45 40 2000 35 30 25 gm (A/V) gm (A/V) 1500 20 Typ +25C Typ +25C 1000 15 500 10 5 0 2.0 0 2.0 3.0 4.0 5.0 6.0 3.0 4.0 5.0 6.0 VDD (Volts) VDD (Volts) DS30430D-page 11-108 1996-2013 Microchip Technology Inc.
PIC16F8X FIGURE 12-17: IOH vs. VOH, VDD = 3 V FIGURE 12-19: IOL vs. VOL, VDD = 3 V 45 0 40 –5 35 30 –10 IOL (mA) IOH (mA) Typ +25C –15 25 Typ +25C 20 15 –20 10 5 –25 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.0 VOH (Volts) 0.5 1.0 1.5 2.0 2.5 3.0 VOL (Volts) FIGURE 12-18: IOH vs. VOH, VDD = 5 V FIGURE 12-20: IOL vs. VOL, VDD = 5 V 90 0 80 –5 70 –10 60 –20 Typ +25C IOL (mA) IOH (mA) –15 Typ +25C 50 40 –25 30 –30 20 –35 10 –40 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.
PIC16F8X FIGURE 12-21: TYPICAL DATA MEMORY ERASE/WRITE CYCLE TIME VS. VDD 10 9 8 DMEM Typ. E/W Cycle Time (ms) 7 6 5 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VDD (Volts) Shaded area is beyond recommended range. TABLE 12-2 INPUT CAPACITANCE* Typical Capacitance (pF) Pin Name 18L PDIP 18L SOIC PORTA 5.0 4.3 PORTB 5.0 4.3 MCLR 17.0 17.0 OSC1/CLKIN 4.0 3.5 OSC2/CLKOUT 4.3 3.5 T0CKI 3.2 2.8 * All capacitance values are typical at 25C.
PIC16F8X 13.0 PACKAGING INFORMATION 13.1 Package Marking Information Example 18L PDIP XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX AABBCDE 18L SOIC Example XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX AABBCDE Legend: XX...
PIC16F8X Package Type: Note: K04-007 18-Lead Plastic Dual In-line (P) – 300 mil For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PIC16F8X Package Type: Note: K04-051 18-Lead Plastic Small Outline (SO) – Wide, 300 mil For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 p E D 2 B 1 n X 45 ° L R2 c A R1 Units Dimension Limits Pitch Number of Pins Overall Pack.
PIC16F8X NOTES: DS30430D-page 114 1996-2013 Microchip Technology Inc.
PIC16F8X APPENDIX A: FEATURE IMPROVEMENTS FROM PIC16C5X TO PIC16F8X The following is the list of feature improvements over the PIC16C5X microcontroller family: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. Instruction word length is increased to 14 bits. This allows larger page sizes both in program memory (2K now as opposed to 512 before) and the register file (128 bytes now versus 32 bytes before). A PC latch register (PCLATH) is added to handle program memory paging.
PIC16F8X APPENDIX C: WHAT’S NEW IN THIS DATA SHEET APPENDIX D: WHAT’S CHANGED IN THIS DATA SHEET Here’s what’s new in this data sheet: Here’s what’s changed in this data sheet: 1. 1. 2. 2. DC & AC Characteristics Graphs/Tables section for PIC16F8X devices has been added. An appendix on conversion considerations has been added. This explains differences for customers wanting to go from PIC16C84 to PIC16F84 or similar device. 3. 4. Errata information has been included.
PIC16F8X APPENDIX E: CONVERSION CONSIDERATIONS - PIC16C84 TO PIC16F83/F84 AND PIC16CR83/CR84 Considerations for converting from the PIC16C84 to the PIC16F84 are listed in the table below. These considerations apply to converting from the PIC16C84 to the PIC16F83 (same as PIC16F84 except for program Difference and data RAM memory sizes) and the PIC16CR84 and PIC16CR83 (ROM versions of Flash devices). Development Systems support is available for all of the PIC16X8X devices.
PIC16F8X NOTES: DS30430D-page 118 1996-2013 Microchip Technology Inc.
PIC16F8X INDEX Numerics 8.1 Configuration Bits ......................................................... 37 A Absolute Maximum Ratings ......................................... 73, 85 ALU ...................................................................................... 7 Architectural Overview ......................................................... 7 Assembler MPASM Assembler .................................................... 70 B Block Diagram Interrupt Logic ....................................
PIC16F8X P Paging, Program Memory .................................................. 18 PCL .............................................................................. 18, 42 PCLATH ....................................................................... 18, 42 PD .......................................................................... 15, 41, 46 PICDEM-1 Low-Cost PIC MCU Demo Board .................... 70 PICDEM-2 Low-Cost PIC16CXX Demo Board ..................
PIC16F8X ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site.
PIC16F8X READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
PIC16F8X PIC16F8X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
PIC16F8X NOTES: DS30430D-page 124 1996-2013 Microchip Technology Inc.
PIC16F8X NOTES: 1996-2013 Microchip Technology Inc.
PIC16F8X DS30430D-page 126 1996-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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