Datasheet

PIC16F818/819
DS39598F-page 82  2001-2013 Microchip Technology Inc.
REGISTER 11-2: ADCON1: A/D CONTROL REGISTER 1 (ADDRESS 9Fh)
R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0
bit 7 ADFM: A/D Result Format Select bit
1 = Right justified, 6 Most Significant bits of ADRESH are read as ‘0’
0 = Left justified, 6 Least Significant bits of ADRESL are read as ‘0’
bit 6 ADCS2: A/D Clock Divide by 2 Select bit
1 = A/D clock source is divided by 2 when system clock is used
0 = Disabled
bit 5-4 Unimplemented: Read as ‘0’
bit 3-0 PCFG<3:0>: A/D Port Configuration Control bits
A = Analog input D = Digital I/O
C/R = Number of analog input channels/Number of A/D voltage references
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PCFG AN4 AN3 AN2 AN1 AN0 VREF+VREF-C/R
0000 AA AAAAV
DD AVSS 5/0
0001 AVREF+ AAAAN3AVSS 4/1
0010 AA AAAAV
DD AVSS 5/0
0011 AVREF+ AAAAN3AVSS 4/1
0100 DA DAAAVDD AVSS 3/0
0101 DV
REF+ DAAAN3AVSS 2/1
011x DD DDDAVDD AVSS 0/0
1000 AVREF+ VREF- AAAN3AN23/2
1001 AA AAAAV
DD AVSS 5/0
1010 AVREF+ AAAAN3AVSS 4/1
1011 AVREF+ VREF- AAAN3AN23/2
1100 AV
REF+ VREF- AAAN3AN23/2
1101 DVREF+ VREF- AAAN3AN22/2
1110 DD DDAAVDD AVSS 1/0
1111 DV
REF+ VREF- DAAN3AN2 1/2