PIC16F818/819 18/20-Pin Enhanced Flash Microcontrollers with nanoWatt Technology Low-Power Features: Pin Diagram • Power-Managed modes: - Primary Run: XT, RC oscillator, 87 A, 1 MHz, 2V - INTRC: 7 A, 31.25 kHz, 2V - Sleep: 0.2 A, 2V • Timer1 oscillator: 1.8 A, 32 kHz, 2V • Watchdog Timer: 0.7 A, 2V • Wide operating voltage range: - Industrial: 2.0V to 5.
PIC16F818/819 Pin Diagrams Note 1: DS39598F-page 2 RA1/AN1 RA0/AN0 NC 23 22 NC 25 24 RA3/AN3/VREF+ RA2/AN2/VREF26 RA4/AN4/T0CKI 27 28-Pin QFN(1) 1 2 3 4 5 6 7 8 9 10 RA2/AN2/VREFRA3/AN3/VREF+ RA4/AN4/T0CKI RA5/MCLR/VPP VSS VSS RB0/INT RB1/SDI/SDA RB2/SDO/CCP1 RB3/CCP1/PGM RA1/AN1 RA0/AN0 RA7/OSC1/CLKI RA6/OSC2/CLKO VDD RB7/T1OSI/PGD RB6/T1OSO/T1CKI/PGC RB5/SS RB4/SCK/SCL 28 18 17 16 15 14 13 12 11 10 20 19 18 17 16 15 14 13 12 11 RA1/AN1 RA0/AN0 RA7/OSC1/CLKI RA6/OSC2/CLKO VDD VDD RB7/
PIC16F818/819 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 5 2.0 Memory Organization ................................................................................................................................................................... 9 3.0 Data EEPROM and Flash Program Memory.........................................................
PIC16F818/819 NOTES: DS39598F-page 4 2001-2013 Microchip Technology Inc.
PIC16F818/819 1.0 DEVICE OVERVIEW This document contains device specific information for the operation of the PIC16F818/819 devices. Additional information may be found in the “PIC® Mid-Range MCU Family Reference Manual” (DS33023) which may be downloaded from the Microchip web site. The Reference Manual should be considered a complementary document to this data sheet and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules.
PIC16F818/819 FIGURE 1-1: PIC16F818/819 BLOCK DIAGRAM 13 Flash Program Memory 1K/2K x 14 Program Bus RAM Addr(1) RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/AN4/T0CKI RA5/MCLR/VPP RA6/OSC2/CLKO RA7/OSC1/CLKI 9 PORTB Addr MUX Instruction reg 7 Direct Addr 8 Indirect Addr FSR reg Status reg 8 3 Power-up Timer Instruction Decode & Control Oscillator Start-up Timer Timing Generation Watchdog Timer Brown-out Reset Power-on Reset RA7/OSC1/CLKI RA6/OSC2/CLKO MCLR RB0/INT RB1/SDI/SDA RB2/SDO/C
PIC16F818/819 TABLE 1-2: PIC16F818/819 PINOUT DESCRIPTIONS Pin Name PDIP/ SSOP QFN SOIC Pin# Pin# Pin# I/O/P Type Buffer Type Description PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 17 RA1/AN1 RA1 AN1 18 RA2/AN2/VREFRA2 AN2 VREF- 1 RA3/AN3/VREF+ RA3 AN3 VREF+ 2 RA4/AN4/T0CKI RA4 AN4 T0CKI 3 RA5/MCLR/VPP RA5 MCLR 4 19 20 1 2 3 4 23 15 17 16 18 Bidirectional I/O pin. Analog input channel 0. I/O I TTL Analog Bidirectional I/O pin. Analog input channel 1.
PIC16F818/819 TABLE 1-2: PIC16F818/819 PINOUT DESCRIPTIONS (CONTINUED) Pin Name PDIP/ SSOP QFN SOIC Pin# Pin# Pin# I/O/P Type Buffer Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.
PIC16F818/819 2.0 MEMORY ORGANIZATION There are two memory blocks in the PIC16F818/819. These are the program memory and the data memory. Each block has its own bus, so access to each block can occur during the same oscillator cycle. The data memory can be further broken down into the general purpose RAM and the Special Function Registers (SFRs). The operation of the SFRs that control the “core” are described here.
PIC16F818/819 2.2 Data Memory Organization The data memory is partitioned into multiple banks that contain the General Purpose Registers and the Special Function Registers. Bits RP1 (Status<6>) and RP0 (Status<5>) are the bank select bits. RP1:RP0 Bank 00 0 01 1 10 2 11 3 Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are the General Purpose Registers, implemented as static RAM.
PIC16F818/819 FIGURE 2-3: PIC16F818 REGISTER FILE MAP File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON ADRESH ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h General Purpose Register File Address Indirect addr.
PIC16F818/819 FIGURE 2-4: PIC16F819 REGISTER FILE MAP File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON ADRESH ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h File Address Indirect addr.
PIC16F818/819 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 2-1. TABLE 2-1: Address Name The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section.
PIC16F818/819 TABLE 2-1: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: Bank 1 80h(1) INDF 81h OPTION_REG 82h(1) PCL 83h(1) STATUS Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE 0000 0000 23 PSA PS2 PS1 PS0 1111 1111 17, 54 0000 0000 23 PD Z DC C 0001 1xxx 16 xxxx xxxx 23 1111 1111 39 1111 1111 43 P
PIC16F818/819 TABLE 2-1: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: Bank 2 100h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 23 101h TMR0 Timer0 Module Register xxxx xxxx 53 102h(1 PCL Program Counter’s (PC) Least Significant Byte 0000 0000 23 103h(1) STATUS 104h(1) FSR 105h RP1 RP0 TO PD Z DC C Indirect
PIC16F818/819 2.2.2.1 Status Register The Status register, shown in Register 2-1, contains the arithmetic status of the ALU, the Reset status and the bank select bits for data memory. The Status register can be the destination for any instruction, as with any other register. If the Status register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic.
PIC16F818/819 2.2.2.2 OPTION_REG Register Note: The OPTION_REG register is a readable and writable register that contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the external INT interrupt, TMR0 and the weak pull-ups on PORTB. REGISTER 2-2: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer.
PIC16F818/819 2.2.2.3 INTCON Register Note: The INTCON register is a readable and writable register that contains various enable and flag bits for the TMR0 register overflow, RB port change and external RB0/INT pin interrupts. REGISTER 2-3: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>).
PIC16F818/819 2.2.2.4 PIE1 Register This register contains the individual enable bits for the peripheral interrupts. Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt.
PIC16F818/819 2.2.2.5 PIR1 Register Note: This register contains the individual flag bits for the peripheral interrupts. REGISTER 2-5: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16F818/819 2.2.2.6 PIE2 Register The PIE2 register contains the individual enable bit for the EEPROM write operation interrupt.
PIC16F818/819 2.2.2.8 Note: PCON Register Note: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent Resets to see if BOR is clear, indicating a brown-out has occurred.
PIC16F818/819 2.3 PCL and PCLATH The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The upper bits (PC<12:8>) are not readable but are indirectly writable through the PCLATH register. On any Reset, the upper bits of the PC will be cleared. Figure 2-5 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH).
PIC16F818/819 FIGURE 2-6: DIRECT/INDIRECT ADDRESSING Direct Addressing RP1:RP0 6 Bank Select Indirect Addressing From Opcode 0 IRP 7 Bank Select Location Select 00 01 10 FSR Register 0 Location Select 11 00h 80h 100h 180h 7Fh FFh 17Fh 1FFh Data Memory(1) Bank 0 Note 1: Bank 1 Bank 2 Bank 3 For register file map detail, see Figure 2-3 or Figure 2-4. DS39598F-page 24 2001-2013 Microchip Technology Inc.
PIC16F818/819 3.0 DATA EEPROM AND FLASH PROGRAM MEMORY The data EEPROM and Flash program memory are readable and writable during normal operation (over the full VDD range). This memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers.
PIC16F818/819 REGISTER 3-1: EECON1: EEPROM ACCESS CONTROL REGISTER 1 (ADDRESS 18Ch) R/W-x U-0 U-0 R/W-x R/W-x R/W-0 R/S-0 R/S-0 EEPGD — — FREE WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: Program/Data EEPROM Select bit 1 = Accesses program memory 0 = Accesses data memory Reads ‘0’ after a POR; this bit cannot be changed while a write operation is in progress.
PIC16F818/819 3.3 Reading Data EEPROM Memory To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit (EECON1<7>) and then set control bit, RD (EECON1<0>). The data is available in the very next cycle in the EEDATA register; therefore, it can be read in the next instruction (see Example 3-1). EEDATA will hold this value until another read or until it is written to by the user (during a write operation).
PIC16F818/819 3.5 Reading Flash Program Memory To read a program memory location, the user must write two bytes of the address to the EEADR and EEADRH registers, set the EEPGD control bit (EECON1<7>) and then set control bit, RD (EECON1<0>). Once the read control bit is set, the program memory Flash controller will use the second instruction cycle to read the data. This causes the second instruction immediately following the “BSF EECON1, RD” instruction to be ignored.
PIC16F818/819 EXAMPLE 3-4: ERASING A FLASH PROGRAM MEMORY ROW BANKSEL MOVF MOVWF MOVF MOVWF EEADRH ADDRH, W EEADRH ADDRL, W EEADR ; Select Bank of EEADRH ; ; MS Byte of Program Address to Erase ; ; LS Byte of Program Address to Erase BANKSEL BSF BSF BSF EECON1 EECON1, EEPGD EECON1, WREN EECON1, FREE ; ; ; ; Select Bank of EECON1 Point to PROGRAM memory Enable Write to memory Enable Row Erase operation BCF MOVLW MOVWF MOVLW MOVWF BSF NOP INTCON, GIE 55h EECON2 AAh EECON2 EECON1, WR ; ; ; ; ; ; ; ;
PIC16F818/819 3.7 Writing to Flash Program Memory The user must follow the same specific sequence to initiate the write for each word in the program block by writing each program word in sequence (00, 01, 10, 11). Flash program memory may only be written to if the destination address is in a segment of memory that is not write-protected, as defined in bits WRT1:WRT0 of the device Configuration Word (Register 12-1). Flash program memory must be written in four-word blocks.
PIC16F818/819 An example of the complete four-word write sequence is shown in Example 3-5. The initial address is loaded into the EEADRH:EEADR register pair; the four words of data are loaded using indirect addressing, assuming that a row erase sequence has already been performed. EXAMPLE 3-5: WRITING TO FLASH PROGRAM MEMORY ; This write routine assumes the following: ; ; ; ; ; ; 1. 2. 3. 4. 5. 6. The 32 words in the erase block have already been erased.
PIC16F818/819 3.8 Protection Against Spurious Write 3.9 There are conditions when the device should not write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built-in. On power-up, WREN is cleared. Also, the Power-up Timer (72 ms duration) prevents an EEPROM write. When the data EEPROM is code-protected, the microcontroller can read and write to the EEPROM normally. However, all external access to the EEPROM is disabled.
PIC16F818/819 4.0 OSCILLATOR CONFIGURATIONS 4.1 Oscillator Types TABLE 4-1: The PIC16F818/819 can be operated in eight different oscillator modes. The user can program three configuration bits (FOSC2:FOSC0) to select one of these eight modes (modes 5-8 are new PIC16 oscillator configurations): 1. 2. 3. 4. LP XT HS RC 5. RCIO 6. INTIO1 7. INTIO2 8. ECIO 4.
PIC16F818/819 FIGURE 4-2: CERAMIC RESONATOR OPERATION (HS OR XT OSC CONFIGURATION) OSC1 PIC16F818/819 C1(1) RES RF(3) Sleep OSC2 RS(2) C2(1) To Internal Logic 4.3 External Clock Input The ECIO Oscillator mode requires an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset or after an exit from Sleep mode. In the ECIO Oscillator mode, the OSC2 pin becomes an additional general purpose I/O pin.
PIC16F818/819 4.4 RC Oscillator 4.5 For timing insensitive applications, the “RC” and “RCIO” device options offer additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal manufacturing variation.
PIC16F818/819 4.5.2 OSCTUNE REGISTER The internal oscillator’s output has been calibrated at the factory but can be adjusted in the application. This is done by writing to the OSCTUNE register (Register 4-1). The tuning sensitivity is constant throughout the tuning range. The OSCTUNE register has a tuning range of ±12.5%. REGISTER 4-1: When the OSCTUNE register is modified, the INTOSC and INTRC frequencies will begin shifting to the new frequency.
PIC16F818/819 4.5.3 OSCILLATOR CONTROL REGISTER The OSCCON register (Register 4-2) controls several aspects of the system clock’s operation. The Internal Oscillator Select bits, IRCF2:IRCF0, select the frequency output of the internal oscillator block that is used to drive the system clock. The choices are the INTRC source (31.25 kHz), the INTOSC source (8 MHz) or one of the six frequencies derived from the INTOSC postscaler (125 kHz to 4 MHz).
PIC16F818/819 FIGURE 4-6: PIC16F818/819 CLOCK DIAGRAM PIC18F818/819 CONFIG (FOSC2:FOSC0) OSC2 Sleep LP, XT, HS, RC, EC OSC1 8 MHz 4 MHz Internal Oscillator Block 111 CPU 110 8 MHz (INTOSC) 1 MHz 100 500 kHz 250 kHz 125 kHz 31.25 kHz 011 MUX 101 31.25 kHz (INTRC) REGISTER 4-2: Internal Oscillator 2 MHz Postscaler 31.
PIC16F818/819 5.0 I/O PORTS Pin RA4 is multiplexed with the Timer0 module clock input and with an analog input to become the RA4/AN4/ T0CKI pin. The RA4/AN4/T0CKI pin is a Schmitt Trigger input and full CMOS output driver. Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Pin RA5 is multiplexed with the Master Clear module input.
PIC16F818/819 FIGURE 5-1: Data Bus BLOCK DIAGRAM OF RA0/AN0:RA1/AN1 PINS FIGURE 5-3: Data Bus D WR PORTA Q CK Q Data Latch D WR TRISA Q I/O pin N Q WR TRISA Analog Input Mode Q N CK Analog Input Mode TTL Input Buffer RD TRISA Q Q I/O pin VSS VSS VSS TTL Input Buffer RD TRISA Q TRIS Latch VSS TRIS Latch VDD VDD P CK Q Data Latch D Q CK D WR PORTA VDD VDD P BLOCK DIAGRAM OF RA2/AN2/VREF- PIN D D EN EN RD PORTA RD PORTA To A/D Module VREF- Input To A/D Module Channel Input T
PIC16F818/819 FIGURE 5-5: BLOCK DIAGRAM OF RA5/MCLR/VPP PIN MCLRE Schmitt Trigger Buffer MCLR Circuit MCLR Filter Data Bus RD TRIS VSS RA5/MCLR/VPP Schmitt Trigger Input Buffer Q VSS D EN MCLRE RD Port FIGURE 5-6: BLOCK DIAGRAM OF RA6/OSC2/CLKO PIN From OSC1 CLKO (FOSC/4) Oscillator Circuit VDD VDD P RA6/OSC2/CLKO Data Bus D WR PORTA Q CK VSS N (FOSC = 1x1) VSS VDD Q P Data Latch D WR TRISA Q N CK Q (FOSC = 1x0,011) TRIS Latch VSS Schmitt Trigger Input Buffer RD TRISA Q D E
PIC16F818/819 FIGURE 5-7: BLOCK DIAGRAM OF RA7/OSC1/CLKI PIN From OSC2 Oscillator Circuit VDD (FOSC = 011) Data Bus D WR PORTA CK Q VDD Q P RA7/OSC1/CLKI VSS Data Latch D WR TRISA Q N CK Q FOSC = 10x TRIS Latch VSS Schmitt Trigger Input Buffer RD TRISA Q D EN FOSC = 10x RD PORTA Note 1: I/O pins have protection diodes to VDD and VSS. DS39598F-page 42 2001-2013 Microchip Technology Inc.
PIC16F818/819 5.2 PORTB and the TRISB Register PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). Each of the PORTB pins has a weak internal pull-up.
PIC16F818/819 TABLE 5-3: PORTB FUNCTIONS Name Bit# Buffer Function RB0/INT bit 0 TTL/ST(1) Input/output pin or external interrupt input. Internal software programmable weak pull-up. RB1/SDI/SDA bit 1 TTL/ST(5) Input/output pin, SPI data input pin or I2C™ data I/O pin. Internal software programmable weak pull-up. RB2/SDO/CCP1 bit 2 TTL/ST(4) Input/output pin, SPI data output pin or Capture input/Compare output/PWM output pin. Internal software programmable weak pull-up.
PIC16F818/819 FIGURE 5-8: BLOCK DIAGRAM OF RB0 PIN VDD RBPU(2) Weak P Pull-up Data Bus WR PORTB Data Latch D Q I/O pin(1) CK TRIS Latch D Q WR TRISB TTL Input Buffer CK RD TRISB Q D RD PORTB EN To INT0 or CCP RD PORTB Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. 2001-2013 Microchip Technology Inc.
PIC16F818/819 FIGURE 5-9: BLOCK DIAGRAM OF RB1 PIN I2C™ Mode Port/SSPEN Select SDA Output 1 0 VDD RBPU(2) Data Bus Weak P Pull-up D WR PORTB VDD Data Latch Q P CK N I/O pin(1) VSS TRIS Latch D Q WR TRISB CK Q RD TRISB TTL Input Buffer SDA Drive Q D RD PORTB EN (3) SDA Schmitt Trigger Buffer RD PORTB SDI Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
PIC16F818/819 FIGURE 5-10: BLOCK DIAGRAM OF RB2 PIN CCPMX Module Select SDO 0 0 CCP 1 1 VDD RBPU(2) Data Bus WR PORTB WR TRISB Weak P Pull-up Data Latch D Q I/O pin(1) CK TRIS Latch D Q TTL Input Buffer CK RD TRISB Q RD PORTB D EN RD PORTB Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. 2001-2013 Microchip Technology Inc.
PIC16F818/819 FIGURE 5-11: BLOCK DIAGRAM OF RB3 PIN CCP1 = 1000, 1001, 11xx and CCPMX = 0 CCP1 = 0100, 0101, 0110, 0111 and CCPMX = 0 CCP 0 or LVP = 1 1 VDD RBPU(2) Data Bus Weak P Pull-up Data Latch D Q WR PORTB I/O pin(1) CK TRIS Latch D Q WR TRISB TTL Input Buffer CK RD TRISB Q D RD PORTB EN To PGM or CCP RD PORTB Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
PIC16F818/819 FIGURE 5-12: BLOCK DIAGRAM OF RB4 PIN Port/SSPEN SCK/SCL 1 0 VDD RBPU(2) Weak P Pull-up VDD SCL Drive P Data Latch Data Bus D WR PORTB Q TRIS Latch D Q WR TRISB I/O pin(1) N CK VSS CK TTL Input Buffer RD TRISB Latch Q D Set RBIF EN RD PORTB From other RB7:RB4 pins Q Q1 D RD PORTB EN Q3 SCK SCL(3) Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
PIC16F818/819 FIGURE 5-13: BLOCK DIAGRAM OF RB5 PIN RBPU(2) VDD Weak P Pull-up Port/SSPEN Data Latch D Q Data Bus WR PORTB I/O pin(1) CK TRIS Latch D Q WR TRISB CK TTL Input Buffer RD TRISB Latch Q D Set RBIF EN RD PORTB From other RB7:RB4 pins Q Q1 D RD PORTB EN Q3 SS Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. DS39598F-page 50 2001-2013 Microchip Technology Inc.
PIC16F818/819 FIGURE 5-14: BLOCK DIAGRAM OF RB6 PIN VDD RBPU(2) Weak P Pull-up Data Latch D Q Data Bus WR PORTB I/O pin(1) CK TRIS Latch D Q WR TRISB CK T1OSCEN RD TRISB T1OSCEN/ICD/ Program Mode TTL Input Buffer Latch Q D Set RBIF EN RD PORTB From other RB7:RB4 pins Q Q1 D RD PORTB EN Q3 T1CKI/PGC From T1OSO Output Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
PIC16F818/819 FIGURE 5-15: BLOCK DIAGRAM OF RB7 PIN Port/Program Mode/ICD PGD 1 0 VDD RBPU(2) Data Bus WR PORTB Weak P Pull-up Data Latch D Q TRIS Latch D Q WR TRISB I/O pin(1) CK CK RD TRISB T1OSCEN PGD DRVEN 0 1 T1OSCEN Analog Input Mode TTL Input Buffer Latch Q D Set RBIF From other RB7:RB4 pins EN RD PORTB Q Q1 D RD PORTB EN Q3 PGD To T1OSI Input Note 1: I/O pins have diode protection to VDD and VSS.
PIC16F818/819 6.0 TIMER0 MODULE Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In Counter mode, Timer0 will increment either on every rising or falling edge of pin RA4/AN4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit, T0SE (OPTION_REG<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.3 “Using Timer0 with an External Clock”.
PIC16F818/819 6.3 Using Timer0 with an External Clock When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, it is necessary for T0CKI to be high for at least 2 TOSC (and a small RC delay of 20 ns) and low for at least 2 TOSC (and a small RC delay of 20 ns).
PIC16F818/819 EXAMPLE 6-1: BANKSEL MOVLW MOVWF BANKSEL CLRF BANKSEL MOVLW MOVWF CLRWDT MOVLW MOVWF CHANGING THE PRESCALER ASSIGNMENT FROM TIMER0 TO WDT OPTION_REG b'xx0x0xxx' OPTION_REG TMR0 TMR0 OPTION_REG b'xxxx1xxx' OPTION_REG CHANGING THE PRESCALER ASSIGNMENT FROM WDT TO TIMER0 CLRWDT BANKSEL OPTION_REG MOVLW b'xxxx0xxx' MOVWF OPTION_REG TABLE 6-1: 01h,101h Select Bank of OPTION_REG Select clock source and prescale value of other than 1:1 Select Bank of TMR0 Clear TMR0 and prescaler Select Bank o
PIC16F818/819 NOTES: DS39598F-page 56 2001-2013 Microchip Technology Inc.
PIC16F818/819 7.0 TIMER1 MODULE The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L) which are readable and writable. The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, TMR1IF (PIR1<0>).
PIC16F818/819 7.2 Timer1 Operation in Timer Mode Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the timer is FOSC/4. The synchronize control bit, T1SYNC (T1CON<2>), has no effect since the internal clock is always in sync. 7.3 Timer1 Counter Operation Timer1 may operate in Asynchronous or Synchronous mode depending on the setting of the TMR1CS bit. When Timer1 is being incremented via an external source, increments occur on a rising edge.
PIC16F818/819 7.5 Timer1 Operation in Asynchronous Counter Mode If control bit, T1SYNC (T1CON<2>), is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and can generate an interrupt on overflow that will wake-up the processor. However, special precautions in software are needed to read/write the timer.
PIC16F818/819 7.6 Timer1 Oscillator A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit, T1OSCEN (T1CON<3>). The oscillator is a low-power oscillator, rated up to 32.768 kHz. It will continue to run during Sleep. It is primarily intended for a 32 kHz crystal. The circuit for a typical LP oscillator is shown in Figure 7-3. Table 7-1 shows the capacitor selection for the Timer1 oscillator.
PIC16F818/819 7.8 Resetting Timer1 Using a CCP Trigger Output If the CCP1 module is configured in Compare mode to generate a “special event trigger” signal (CCP1M3:CCP1M0 = 1011), the signal will reset Timer1 and start an A/D conversion (if the A/D module is enabled). Timer1 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature. If Timer1 is running in Asynchronous Counter mode, this Reset operation may not work.
PIC16F818/819 EXAMPLE 7-3: RTCinit BANKSEL MOVLW MOVWF CLRF MOVLW MOVWF CLRF CLRF MOVLW MOVWF BANKSEL BSF RETURN BANKSEL BSF BCF INCF MOVF SUBLW BTFSS RETURN CLRF INCF MOVF SUBLW BTFSS RETURN CLRF INCF MOVF SUBLW BTFSS RETURN CLRF RETURN RTCisr TABLE 7-2: Address IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE TMR1H TMR1H, 7 PIR1, TMR1IF secs, F secs, w .60 STATUS, Z seconds mins, f mins, w .60 STATUS, Z mins hours, f hours, w .
PIC16F818/819 8.0 TIMER2 MODULE Timer2 is an 8-bit timer with a prescaler and a postscaler. It can be used as the PWM time base for the PWM mode of the CCP1 module. The TMR2 register is readable and writable and is cleared on any device Reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits, T2CKPS1:T2CKPS0 (T2CON<1:0>). The Timer2 module has an 8-bit period register, PR2.
PIC16F818/819 REGISTER 8-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h) U-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale 0010 = 1:3 Postscale • • • 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bit
PIC16F818/819 9.0 CAPTURE/COMPARE/PWM (CCP) MODULE The CCP module’s input/output pin (CCP1) can be configured as RB2 or RB3. This selection is set in bit 12 (CCPMX) of the Configuration Word register. The Capture/Compare/PWM (CCP) module contains a 16-bit register that can operate as a: • 16-bit Capture register • 16-bit Compare register • PWM Master/Slave Duty Cycle register Table 9-1 shows the timer resources of the CCP module modes.
PIC16F818/819 9.1 9.1.2 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on the CCP1 pin. An event is defined as: • • • • Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge 9.1.1 CCP PIN CONFIGURATION In Capture mode, the CCP1 pin should be configured as an input by setting the TRISB bit. Note 1: If the CCP1 pin is configured as an output, a write to the port can cause a capture condition.
PIC16F818/819 9.2 9.2.1 Compare Mode CCP PIN CONFIGURATION The user must configure the CCP1 pin as an output by clearing the TRISB bit. In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the CCP1 pin is: Note 1: Clearing the CCP1CON register will force the CCP1 compare output latch to the default low level. This is not the data latch.
PIC16F818/819 9.3 9.3.1 PWM Mode In Pulse-Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTB data latch, the TRISB bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTB I/O data latch. Figure 9-3 shows a simplified block diagram of the CCP module in PWM mode.
PIC16F818/819 9.3.3 The maximum PWM resolution (bits) for a given PWM frequency is given by the following formula. The following steps should be taken when configuring the CCP module for PWM operation: EQUATION 9-3: FOSC log FPWM ( Resolution = Note: log(2) SETUP FOR PWM OPERATION 1. 2. ) bits 3. If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared. 4. 5. Set the PWM period by writing to the PR2 register.
PIC16F818/819 NOTES: DS39598F-page 70 2001-2013 Microchip Technology Inc.
PIC16F818/819 10.0 10.1 SYNCHRONOUS SERIAL PORT (SSP) MODULE SSP Module Overview The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc.
PIC16F818/819 REGISTER 10-1: SSPSTAT: SYNCHRONOUS SERIAL PORT STATUS REGISTER (ADDRESS 94h) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: SPI Data Input Sample Phase bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time (Microwire) SPI Slave mode: This bit must be cleared when SPI is used in Slave mode. I2 C mode: This bit must be maintained clear.
PIC16F818/819 REGISTER 10-2: SSPCON: SYNCHRONOUS SERIAL PORT CONTROL REGISTER 1 (ADDRESS 14h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit 1 = An attempt to write the SSPBUF register failed because the SSP module is busy (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit In SPI mode: 1 = A new byte is received while the SSPBUF register is still hold
PIC16F818/819 FIGURE 10-1: SSP BLOCK DIAGRAM (SPI MODE) To enable the serial port, SSP Enable bit, SSPEN (SSPCON<5>), must be set. To reset or reconfigure SPI mode, clear bit SSPEN, reinitialize the SSPCON register and then set bit SSPEN. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, they must have their data direction bits (in the TRISB register) appropriately programmed.
PIC16F818/819 FIGURE 10-2: SPI MODE TIMING, MASTER MODE SCK (CKP = 0, CKE = 0) SCK (CKP = 0, CKE = 1) SCK (CKP = 1, CKE = 0) SCK (CKP = 1, CKE = 1) bit 7 SDO bit 6 bit 5 bit 2 bit 3 bit 4 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 SDI (SMP = 1) bit 7 bit 0 SSPIF FIGURE 10-3: SPI MODE TIMING (SLAVE MODE WITH CKE = 0) SS (Optional) SCK (CKP = 0) SCK (CKP = 1) bit 7 SDO bit 6 bit 5 bit 2 bit 3 bit 4 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 SSPIF FIGURE 10-4: SPI MODE TIMING (SLAVE MODE
PIC16F818/819 10.3 SSP I 2C Mode Operation The SSP module in I 2C mode fully implements all slave functions, except general call support and provides interrupts on Start and Stop bits in hardware to facilitate firmware implementations of the master functions. The SSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. Two pins are used for data transfer. These are the RB4/SCK/SCL pin, which is the clock (SCL) and the RB1/SDI/SDA pin, which is the data (SDA).
PIC16F818/819 10.3.1 SLAVE MODE In Slave mode, the SCL and SDA pins must be configured as inputs (TRISB<4,1> set). The SSP module will override the input state with the output data when required (slave-transmitter). The sequence of events for 10-bit address is as follows, with steps 7-9 for slave-transmitter: 1. 2.
PIC16F818/819 An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF must be cleared in software and the SSPSTAT register is used to determine the status of the byte. Flag bit SSPIF is set on the falling edge of the ninth clock pulse. the data transfer is complete. When the ACK is latched by the slave device, the slave logic is reset (resets SSPSTAT register) and the slave device then monitors for another occurrence of the Start bit.
PIC16F818/819 10.3.2 MASTER MODE OPERATION 10.3.3 Master mode operation is supported in firmware using interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the SSP module is disabled. The Stop (P) and Start (S) bits will toggle based on the Start and Stop conditions. Control of the I 2C bus may be taken when the P bit is set or the bus is Idle and both the S and P bits are clear.
PIC16F818/819 NOTES: DS39598F-page 80 2001-2013 Microchip Technology Inc.
PIC16F818/819 11.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The A/D module has four registers: The Analog-to-Digital (A/D) converter module has five inputs for 18/20 pin devices. The conversion of an analog input signal results in a corresponding 10-bit digital number. The A/D module has a high and low-voltage reference input that is software selectable to some combination of VDD, VSS, RA2 or RA3. The A/D converter has a unique feature of being able to operate while the device is in Sleep mode.
PIC16F818/819 REGISTER 11-2: ADCON1: A/D CONTROL REGISTER 1 (ADDRESS 9Fh) R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified, 6 Most Significant bits of ADRESH are read as ‘0’ 0 = Left justified, 6 Least Significant bits of ADRESL are read as ‘0’ bit 6 ADCS2: A/D Clock Divide by 2 Select bit 1 = A/D clock source is divided by 2 when system clock is used 0 = Disabled bit 5-4 Unimpl
PIC16F818/819 The ADRESH:ADRESL registers contain the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the A/D Result register pair, the GO/DONE bit (ADCON0<2>) is cleared and A/D Interrupt Flag bit, ADIF, is set. The block diagram of the A/D module is shown in Figure 11-1. These steps should be followed for doing an A/D conversion: 1. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started.
PIC16F818/819 11.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 11-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 11-2.
PIC16F818/819 11.2 Selecting the A/D Conversion Clock The A/D conversion time per bit is defined as TAD. The A/D conversion requires 9.0 TAD per 10-bit conversion. The source of the A/D conversion clock is software selectable.
PIC16F818/819 11.4 11.4.1 A/D Conversions A/D RESULT REGISTERS The ADRESH:ADRESL register pair is the location where the 10-bit A/D result is loaded at the completion of the A/D conversion. This register pair is 16 bits wide. The A/D module gives the flexibility to left or right justify the 10-bit result in the 16-bit result register. The A/D Format Select bit (ADFM) controls this justification. Figure 11-4 shows the operation of the A/D result justification. The extra bits are loaded with ‘0’s.
PIC16F818/819 11.5 A/D Operation During Sleep 11.6 The A/D module can operate during Sleep mode. This requires that the A/D clock source be set to RC (ADCS1:ADCS0 = 11). When the RC clock source is selected, the A/D module waits one instruction cycle before starting the conversion. This allows the SLEEP instruction to be executed which eliminates all digital switching noise from the conversion.
PIC16F818/819 NOTES: DS39598F-page 88 2001-2013 Microchip Technology Inc.
PIC16F818/819 12.
PIC16F818/819 REGISTER 12-1: R/P-1 R/P-1 CONFIGURATION WORD (ADDRESS 2007h)(1) R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 CP CCPMX DEBUG WRT1 WRT0 CPD bit 13 bit 13 bit 12 bit 11 bit 10-9 bit 8 bit 7 bit 6 bit 5 bit 3 bit 2 bit 4, 1-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 LVP BOREN MCLRE FOSC2 PWRTEN WDTEN FOSC1 FOSC0 bit 0 CP: Flash Program Memory Code Protection bit 1 = Code protection off 0 = All memory locations code-protected CCPMX: CCP1 Pin Selection bit 1 = CCP1 function on RB2 0 = CCP
PIC16F818/819 12.2 Reset The PIC16F818/819 differentiates between various kinds of Reset: • • • • • • Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during Sleep WDT Reset during normal operation WDT wake-up during Sleep Brown-out Reset (BOR) Some registers are not affected in any Reset condition. Their status is unknown on POR and unchanged in any other Reset.
PIC16F818/819 12.3 MCLR 12.5 PIC16F818/819 device has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. The behavior of the ESD protection on the MCLR pin has been altered from previous devices of this family. Voltages applied to the pin that exceed its specification can result in both MCLR and excessive current beyond the device specification during the ESD event.
PIC16F818/819 12.9 Power Control/Status Register (PCON) bit BOR cleared, indicating a Brown-out Reset occurred. When the Brown-out Reset is disabled, the state of the BOR bit is unpredictable. The Power Control/Status register, PCON, has two bits to indicate the type of Reset that last occurred. Bit 1 is Power-on Reset Status bit, POR. It is cleared on a Power-on Reset and unaffected otherwise. The user must set this bit following a Power-on Reset. Bit 0 is Brown-out Reset Status bit, BOR.
PIC16F818/819 TABLE 12-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS Power-on Reset, Brown-out Reset MCLR Reset, WDT Reset Wake-up via WDT or Interrupt W xxxx xxxx uuuu uuuu uuuu uuuu INDF N/A N/A N/A TMR0 xxxx xxxx uuuu uuuu uuuu uuuu PCL 0000h 0000h PC + 1(2) STATUS 0001 1xxx 000q quuu(3) uuuq quuu(3) FSR xxxx xxxx uuuu uuuu uuuu uuuu PORTA xxx0 0000 uuu0 0000 uuuu uuuu PORTB xxxx xxxx uuuu uuuu uuuu uuuu PCLATH ---0 0000 ---0 0000 ---u uuuu INTCON 0000 000x 0000 000u uuuu uuuu(1) PIR1 -0--
PIC16F818/819 FIGURE 12-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH PULL-UP RESISTOR) VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 12-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH RC NETWORK): CASE 1 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 12-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH RC NETWORK): CASE 2 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out
PIC16F818/819 FIGURE 12-6: SLOW RISE TIME (MCLR TIED TO VDD THROUGH RC NETWORK) 5V VDD 1V 0V MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset 12.10 Interrupts The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register. The PIC16F818/819 has up to nine sources of interrupt. The Interrupt Control register (INTCON) records individual interrupt requests in flag bits.
PIC16F818/819 12.10.1 INT INTERRUPT 12.10.3 External interrupt on the RB0/INT pin is edge triggered, either rising if bit INTEDG (OPTION_REG<6>) is set, or falling if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, flag bit, INTF (INTCON<1>), is set. This interrupt can be disabled by clearing enable bit, INTE (INTCON<4>). Flag bit INTF must be cleared in software in the Interrupt Service Routine before re-enabling this interrupt.
PIC16F818/819 12.12 Watchdog Timer (WDT) WDT time-out period values may be found in Section 15.0 “Electrical Characteristics” under parameter #31. Values for the WDT prescaler (actually a postscaler but shared with the Timer0 prescaler) may be assigned using the OPTION_REG register. For PIC16F818/819 devices, the WDT is driven by the INTRC oscillator. When the WDT is enabled, the INTRC (31.25 kHz) oscillator is enabled. The nominal WDT period is 16 ms and has the same accuracy as the INTRC oscillator.
PIC16F818/819 12.13 Power-Down Mode (Sleep) Power-Down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (Status<3>) is cleared, the TO (Status<4>) bit is set and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, low or high-impedance).
PIC16F818/819 FIGURE 12-9: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKO(4) INT pin INTF Flag (INTCON<1>) Interrupt Latency (Note 2) GIE bit (INTCON<7>) Processor in Sleep INSTRUCTION FLOW PC PC Instruction Inst(PC) = Sleep Fetched Instruction Inst(PC – 1) Executed Note 1: 2: 3: 4: PC + 1 PC + 2 PC + 2 Inst(PC + 1) Inst(PC + 2) Sleep Inst(PC + 1) PC + 2 Dummy Cycle 0004h 0005h Inst(0004h) Inst(0005h)
PIC16F818/819 12.17 In-Circuit Serial Programming PIC16F818/819 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for power, ground and the programming voltage (see Figure 12-10 for an example). This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product.
PIC16F818/819 12.18 Low-Voltage ICSP Programming The LVP bit of the Configuration Word register enables Low-Voltage ICSP Programming. This mode allows the microcontroller to be programmed via ICSP using a VDD source in the operating voltage range. This only means that VPP does not have to be brought to VIHH but can instead be left at the normal operating voltage. In this mode, the RB3/PGM pin is dedicated to the programming function and ceases to be a general purpose I/O pin.
PIC16F818/819 13.0 INSTRUCTION SET SUMMARY The PIC16 instruction set is highly orthogonal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction.
PIC16F818/819 TABLE 13-2: PIC16F818/819 INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f
PIC16F818/819 13.2 Instruction Descriptions ADDLW Add Literal and W ANDWF AND W with f Syntax: [ label ] ADDLW Syntax: [ label ] ANDWF Operands: 0 k 255 Operands: 0 f 127 d [0,1] Operation: (W) + k (W) Status Affected: C, DC, Z Operation: (W) .AND. (f) (destination) Description: The contents of the W register are added to the eight-bit literal ‘k’ and the result is placed in the W register. Status Affected: Z Description: AND the W register with register ‘f’.
PIC16F818/819 BTFSS Bit Test f, Skip if Set CLRF Clear f Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRF Operands: 0 f 127 0b<7 Operands: 0 f 127 Operation: Operation: skip if (f) = 1 00h (f) 1Z Status Affected: None Status Affected: Z Description: If bit ‘b’ in register ‘f’ = 0, the next instruction is executed. If bit ‘b’ = 1, then the next instruction is discarded and a NOP is executed instead, making this a 2 TCY instruction.
PIC16F818/819 COMF Complement f Syntax: [ label ] COMF GOTO Unconditional Branch Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 k 2047 Operation: (f) (destination) Operation: k PC<10:0> PCLATH<4:3> PC<12:11> Status Affected: Z Status Affected: None Description: The contents of register ‘f’ are complemented. If ‘d’ = 0, the result is stored in W. If ‘d’ = 1, the result is stored back in register ‘f’. Description: GOTO is an unconditional branch.
PIC16F818/819 IORLW Inclusive OR Literal with W MOVLW Move Literal to W Syntax: [ label ] Syntax: [ label ] Operands: 0 k 255 Operands: 0 k 255 Operation: (W) .OR. k (W) Operation: k (W) Status Affected: Z Status Affected: None Description: The contents of the W register are ORed with the eight-bit literal ‘k’. The result is placed in the W register. Description: The eight-bit literal ‘k’ is loaded into W register. The don’t cares will assemble as ‘0’s.
PIC16F818/819 RETFIE Return from Interrupt RLF Rotate Left f through Carry Syntax: [ label ] Syntax: [ label ] Operands: None Operands: Operation: TOS PC, 1 GIE 0 f 127 d [0,1] Operation: See description below Status Affected: None Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ = 0, the result is placed in the W register. If ‘d’ = 1, the result is stored back in register ‘f’.
PIC16F818/819 SUBLW Syntax: Subtract W from Literal [ label ] SUBLW k XORLW Exclusive OR Literal with W Syntax: [ label ] XORLW k Operands: 0 k 255 Operands: 0 k 255 Operation: k – (W) W) Operation: (W) .XOR. k W) Status Affected: C, DC, Z Status Affected: Z Description: The W register is subtracted (2’s complement method) from the eight-bit literal ‘k’. The result is placed in the W register.
PIC16F818/819 14.
PIC16F818/819 14.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 14.
PIC16F818/819 14.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC16F818/819 14.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 14.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC16F818/819 15.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Ambient temperature under bias............................................................................................................ -40°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD and MCLR) ................................................... -0.
PIC16F818/819 FIGURE 15-1: PIC16F818/819 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL, EXTENDED) 6.0V 5.5V Voltage 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V 16 MHz 20 MHz Frequency FIGURE 15-2: PIC16LF818/819 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V 4 MHz 10 MHz Frequency FMAX = (12 MHz/V) (VDDAPPMIN – 2.5V) + 4 MHz Note 1: VDDAPPMIN is the minimum voltage of the PIC® device in the application. Note 2: FMAX has a maximum frequency of 10 MHz.
PIC16F818/819 15.1 DC Characteristics: Supply Voltage PIC16F818/819 (Industrial, Extended) PIC16LF818/819 (Industrial) PIC16LF818/819 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC16F818/819 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No.
PIC16F818/819 15.2 DC Characteristics: Power-Down and Supply Current PIC16F818/819 (Industrial, Extended) PIC16LF818/819 (Industrial) PIC16LF818/819 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC16F818/819 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No.
PIC16F818/819 15.2 DC Characteristics: Power-Down and Supply Current PIC16F818/819 (Industrial, Extended) PIC16LF818/819 (Industrial) (Continued) PIC16LF818/819 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC16F818/819 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No.
PIC16F818/819 15.2 DC Characteristics: Power-Down and Supply Current PIC16F818/819 (Industrial, Extended) PIC16LF818/819 (Industrial) (Continued) PIC16LF818/819 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC16F818/819 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No.
PIC16F818/819 15.2 DC Characteristics: Power-Down and Supply Current PIC16F818/819 (Industrial, Extended) PIC16LF818/819 (Industrial) (Continued) PIC16LF818/819 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC16F818/819 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No.
PIC16F818/819 15.2 DC Characteristics: Power-Down and Supply Current PIC16F818/819 (Industrial, Extended) PIC16LF818/819 (Industrial) (Continued) PIC16LF818/819 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC16F818/819 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No.
PIC16F818/819 15.2 DC Characteristics: Power-Down and Supply Current PIC16F818/819 (Industrial, Extended) PIC16LF818/819 (Industrial) (Continued) PIC16LF818/819 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC16F818/819 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No.
PIC16F818/819 15.2 DC Characteristics: Power-Down and Supply Current PIC16F818/819 (Industrial, Extended) PIC16LF818/819 (Industrial) (Continued) PIC16LF818/819 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC16F818/819 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No.
PIC16F818/819 15.
PIC16F818/819 15.4 DC Characteristics: PIC16F818/819 (Industrial, Extended) PIC16LF818/819 (Industrial) DC CHARACTERISTICS Param No. Sym VIL Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Operating voltage VDD range as described in Section 15.1 “DC Characteristics: Supply Voltage”. Characteristic Min Typ† Max Units Conditions with TTL buffer VSS — 0.15 VDD V For entire VDD range VSS — 0.
PIC16F818/819 15.4 DC Characteristics: PIC16F818/819 (Industrial, Extended) PIC16LF818/819 (Industrial) (Continued) DC CHARACTERISTICS Param No. Sym VOL Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Operating voltage VDD range as described in Section 15.1 “DC Characteristics: Supply Voltage”. Min Typ† Max Units Conditions Output Low Voltage D080 I/O ports — — 0.6 V IOL = 8.
PIC16F818/819 15.5 Timing Parameter Symbology The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4.
PIC16F818/819 FIGURE 15-4: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKO TABLE 15-1: Param No. Sym FOSC EXTERNAL CLOCK TIMING REQUIREMENTS Characteristic External CLKI Frequency (Note 1) Oscillator Frequency (Note 1) 1 TOSC External CLKI Period (Note 1) Oscillator Period (Note 1) Min Typ† Max Units Conditions DC — 1 MHz XT and RC Oscillator mode DC — 20 MHz HS Oscillator mode DC — 32 kHz DC — 4 MHz RC Oscillator mode 0.
PIC16F818/819 FIGURE 15-5: CLKO AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKO 13 19 14 12 18 16 I/O pin (Input) 15 17 I/O pin (Output) New Value Old Value 20, 21 Note: Refer to Figure 15-3 for load conditions. TABLE 15-2: Param No.
PIC16F818/819 FIGURE 15-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 Oscillator Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure 15-3 for load conditions. FIGURE 15-7: BROWN-OUT RESET TIMING VBOR VDD 35 TABLE 15-3: Param No.
PIC16F818/819 FIGURE 15-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 RB6/T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 15-3 for load conditions. TABLE 15-4: Param No.
PIC16F818/819 FIGURE 15-9: CAPTURE/COMPARE/PWM TIMINGS (CCP1) CCP1 (Capture Mode) 51 50 52 CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure 15-3 for load conditions. TABLE 15-5: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1) Param Symbol No. 50* TCCL Characteristic CCP1 No Prescaler Input Low Time 0.
PIC16F818/819 FIGURE 15-10: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 Bit 6 - - - - - -1 MSb SDO LSb 75, 76 SDI Bit 6 - - - -1 MSb In LSb In 74 73 Note: Refer to Figure 15-3 for load conditions. FIGURE 15-11: SPI MASTER MODE TIMING (CKE = 1, SMP = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 SDO MSb Bit 6 - - - - - -1 LSb Bit 6 - - - -1 LSb In 75, 76 SDI MSb In 74 Note: Refer to Figure 15-3 for load conditions.
PIC16F818/819 FIGURE 15-12: SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 72 71 78 79 79 78 SCK (CKP = 1) 80 Bit 6 - - - - - -1 MSb SDO LSb 77 75, 76 MSb In SDI Bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure 15-3 for load conditions. FIGURE 15-13: SPI SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 SDO MSb Bit 6 - - - - - -1 LSb 75, 76 SDI MSb In 77 Bit 6 - - - -1 LSb In 74 Note: Refer to Figure 15-3 for load conditions.
PIC16F818/819 TABLE 15-6: Param No.
PIC16F818/819 TABLE 15-7: Param No.
PIC16F818/819 TABLE 15-8: Param. No. 100* I2C™ BUS DATA REQUIREMENTS Symbol THIGH Characteristic Clock High Time 100 kHz mode 400 kHz mode TLOW Clock Low Time TR 103* TF 90* TSU:STA THD:STA 91* 106* THD:DAT TSU:DAT 107* TSU:STO 92* 109* TAA 110* TBUF CB * Note 1: 2: Units 4.0 — s s 0.6 — — 100 kHz mode 4.7 — s 400 kHz mode 1.3 — s SSP Module 102* Max 1.5 TCY SSP Module 101* Min SDA and SCL Rise 100 kHz mode Time 400 kHz mode 1.5 TCY — — 1000 ns 20 + 0.
PIC16F818/819 TABLE 15-9: Param Sym No. A/D CONVERTER CHARACTERISTICS: PIC16F818/819 (INDUSTRIAL, EXTENDED) PIC16LF818/819 (INDUSTRIAL) Characteristic Min Typ† Max Units Conditions A01 NR Resolution — — 10-bits bit VREF = VDD = 5.12V, VSS VAIN VREF A03 EIL Integral Linearity Error — — <±1 LSb VREF = VDD = 5.12V, VSS VAIN VREF A04 EDL Differential Linearity Error — — <±1 LSb VREF = VDD = 5.12V, VSS VAIN VREF A06 EOFF Offset Error — — <±2 LSb VREF = VDD = 5.
PIC16F818/819 FIGURE 15-16: A/D CONVERSION TIMING 1 TCY BSF ADCON0, GO (TOSC/2)(1) 131 Q4 130 132 A/D CLK 9 A/D DATA 8 7 2 1 0 NEW_DATA OLD_DATA ADRES ADIF GO DONE Sampling Stopped SAMPLE Note: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 15-10: A/D CONVERSION REQUIREMENTS Param Symbol No. 130 TAD Characteristic A/D Clock Period — — s TOSC based, VREF 3.
PIC16F818/819 16.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
PIC16F818/819 FIGURE 16-3: TYPICAL IDD vs. FOSC OVER VDD (XT MODE) 1.8 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 1.6 5.5V 1.4 5.0V 1.2 4.5V IDD (mA) 4.0V 1.0 3.5V 0.8 3.0V 2.5V 0.6 2.0V 0.4 0.2 0.0 0 500 1000 1500 2000 2500 3000 3500 4000 3500 4000 FOSC (MHz) FIGURE 16-4: MAXIMUM IDD vs. FOSC OVER VDD (XT MODE) 2.
PIC16F818/819 FIGURE 16-5: TYPICAL IDD vs. FOSC OVER VDD (LP MODE) 70 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 60 5.5V 5.0V 50 4.5V IDD (uA) 40 4.0V 3.5V 30 3.0V 2.5V 20 2.0V 10 0 20 30 40 50 60 70 80 90 100 FOSC (kHz) FIGURE 16-6: MAXIMUM IDD vs. FOSC OVER VDD (LP MODE) 120 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 100 5.5V 5.0V 4.
PIC16F818/819 FIGURE 16-7: TYPICAL IDD vs. VDD, -40C TO +125C, 1 MHz TO 8 MHz (RC_RUN MODE, ALL PERIPHERALS DISABLED) 1.6 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 1.4 5.5V 5.0V 1.2 4.5V 1.0 IDD (mA) 4.0V 3.5V 0.8 3.0V 0.6 2.5V 0.4 2.0V 0.2 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 FOSC (MHz) FIGURE 16-8: MAXIMUM IDD vs. VDD, -40C TO +125C, 1 MHz TO 8 MHz (RC_RUN MODE, ALL PERIPHERALS DISABLED) 4.
PIC16F818/819 FIGURE 16-9: IPD vs. VDD, -40C TO +125C (SLEEP MODE, ALL PERIPHERALS DISABLED) 100 Max (125°C) 10 Max (85°C) IPD (uA) 1 0.1 0.01 Typ (25°C) Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 0.001 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-10: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 20 pF, +25C) 4.5 Operation above 4 MHz is not recommended 4.0 5.1 kOhm 3.5 Freq (MHz) 3.0 2.5 10 kOhm 2.
PIC16F818/819 FIGURE 16-11: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 100 pF, +25C) 2.5 2.0 3.3 kOhm Freq (MHz) 1.5 5.1 kOhm 1.0 10 kOhm 0.5 100 kOhm 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.0 5.5 VDD (V) FIGURE 16-12: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 300 pF, +25C) 0.9 0.8 3.3 kOhm 0.7 0.6 Freq (MHz) 5.1 kOhm 0.5 0.4 10 kOhm 0.3 0.2 0.1 100 kOhm 0.0 2.0 2.5 3.0 3.5 4.0 4.
PIC16F818/819 FIGURE 16-13: IPD TIMER1 OSCILLATOR, -10°C TO +70°C (SLEEP MODE, TMR1 COUNTER DISABLED) 5.0 4.5 Max (-10°C to +70°C) 4.0 3.5 3.0 IPD (A) Typ (+25°C) 2.5 2.0 1.5 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC16F818/819 FIGURE 16-15: IPD BOR vs. VDD, -40°C TO +125°C (SLEEP MODE, BOR ENABLED AT 2.00V-2.16V) 1,000 Max (125°C) Typ (25°C) Device in Sleep IDD (A) Indeterminant State Device in Reset 100 Note: Device current in Reset depends on oscillator mode, frequency and circuit. Max (125°C) Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) Typ (25°C) 10 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC16F818/819 FIGURE 16-17: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40C TO +125C) 5.5 5.0 4.5 4.0 Max 3.5 VOH (V) Typ (25°C) 3.0 2.5 Min 2.0 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 1.5 1.0 0.5 0.0 0 5 10 15 20 25 IOH (-mA) FIGURE 16-18: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40C TO +125C) 3.
PIC16F818/819 FIGURE 16-19: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 5V, -40C TO +125C) 1.0 0.9 Max (125°C) Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 0.8 0.7 Max (85°C) VOL (V) 0.6 0.5 Typ (25°C) 0.4 0.3 Min (-40°C) 0.2 0.1 0.0 0 5 10 15 20 25 IOL (-mA) FIGURE 16-20: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 3V, -40C TO +125C) 3.
PIC16F818/819 FIGURE 16-21: MINIMUM AND MAXIMUM VIN vs. VDD (TTL INPUT, -40C TO +125C) 1.5 1.4 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 1.3 VTH Max (-40°C) 1.2 1.1 VIN (V) VTH Typ (25°C) 1.0 VTH Min (125°C) 0.9 0.8 0.7 0.6 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-22: MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40C TO +125C) 4.
PIC16F818/819 MINIMUM AND MAXIMUM VIN vs. VDD (I2C™ INPUT, -40C TO +125C) FIGURE 16-23: 3.5 VIH Max Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 3.0 2.5 2.0 VIN (V) V Max VIL ILMax VIH Min 1.5 1.0 VIL Min 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) A/D NONLINEARITY vs. VREFH (VDD = VREFH, -40C TO +125C) FIGURE 16-24: 4 3.5 Differential or Integral Nonlinearity (LSB) -40°C -40C 3 +25°C 25C 2.5 +85°C 85C 2 1.
PIC16F818/819 FIGURE 16-25: A/D NONLINEARITY vs. VREFH (VDD = 5V, -40C TO +125C) 3 Differential or Integral Nonlinearilty (LSB) 2.5 2 1.5 Max +125°C) Max (-40°C (-40C toto125C) 1 Typ Typ (+25°C) (25C) 0.5 0 2 2.5 3 3.5 4 4.5 5 5.5 VREFH (V) 2001-2013 Microchip Technology Inc.
PIC16F818/819 NOTES: DS39598F-page 154 2001-2013 Microchip Technology Inc.
PIC16F818/819 17.0 PACKAGING INFORMATION 17.1 Package Marking Information 18-Lead PDIP (300 mil) Example PIC16F818-I/P 0410017 e3 18-Lead SOIC 18-Lead SOIC (7.50 mm) Example PIC16F818-04 /SO e3 0410017 20-Lead SSOP (5.30 mm) Example PIC16F81820/SS e3 0410017 28-Lead QFN (6x6 mm) PIN 1 XXXXXXXX XXXXXXXX YYWWNNN Legend: XX...
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PIC16F818/819 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2001-2013 Microchip Technology Inc.
PIC16F818/819 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39598F-page 158 2001-2013 Microchip Technology Inc.
PIC16F818/819 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2001-2013 Microchip Technology Inc.
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PIC16F818/819 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2001-2013 Microchip Technology Inc.
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PIC16F818/819 /HDG 3ODVWLF 4XDG )ODW 1R /HDG 3DFNDJH 0/ ± [ PP %RG\ >4)1@ ZLWK PP &RQWDFW /HQJWK 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ 2001-2013 Microchip Technology Inc.
PIC16F818/819 NOTES: DS39598F-page 164 2001-2013 Microchip Technology Inc.
PIC16F818/819 APPENDIX A: REVISION HISTORY Revision A (May 2002) Original version of this data sheet. Revision B (August 2002) Added INTRC section. PWRT and BOR are independent of each other. Revised program memory text and code routine. Added QFN package. Modified PORTB diagrams. Revision D (November 2003) Updated IRCF bit modification information and changed the INTOSC stabilization delay from 1 ms to 4 ms in Section 4.0 “Oscillator Configurations”. Updated Section 12.
PIC16F818/819 NOTES: DS39598F-page 166 2001-2013 Microchip Technology Inc.
PIC16F818/819 INDEX A A/D Acquisition Requirements .......................................... 84 ADIF Bit ...................................................................... 83 Analog-to-Digital Converter ........................................ 81 Associated Registers ................................................. 87 Calculating Acquisition Time ...................................... 84 Configuring Analog Port Pins ..................................... 85 Configuring the Interrupt ...................
PIC16F818/819 Writing to Flash Program Memory ............................. 31 Code Protection ......................................................... 89, 100 Computed GOTO ............................................................... 23 Configuration Bits ............................................................... 89 Crystal Oscillator and Ceramic Resonators ....................... 33 Customer Change Notification Service ............................ 173 Customer Notification Service ...............
PIC16F818/819 TMR0IE Bit ................................................................. 18 Internal Oscillator Block ..................................................... 35 INTRC Modes ............................................................ 35 Internet Address ............................................................... 173 Interrupt Sources .......................................................... 89, 96 RB0/INT Pin, External ................................................ 97 TMR0 Overflow ..
PIC16F818/819 Program Memory Interrupt Vector ............................................................ 9 Map and Stack PIC16F818 ........................................................... 9 PIC16F819 ........................................................... 9 Reset Vector ................................................................ 9 Program Verification ......................................................... 100 PUSH .............................................................................
PIC16F818/819 Timer1 ................................................................................ 57 Associated Registers ................................................. 62 Capacitor Selection .................................................... 60 Counter Operation ..................................................... 58 Operation ................................................................... 57 Operation in Asynchronous Counter Mode ................ 59 Operation in Synchronized Counter Mode ...
PIC16F818/819 NOTES: DS39598F-page 172 2001-2013 Microchip Technology Inc.
PIC16F818/819 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC16F818/819 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC16F818/819 PIC16F818/819 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX XXX Package Pattern Examples: a) b) Device PIC16F818: Standard VDD range PIC16F818T: (Tape and Reel) PIC16LF818: Extended VDD range Temperature Range - = I = E = Package P SO SS ML PIC16LF818-I/P = Industrial temp., PDIP package, Extended VDD limits. PIC16F818-I/SO = Industrial temp.
PIC16F818/819 NOTES: DS39598F-page 176 2001-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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