Datasheet

PIC16F818/819
DS39598F-page 74  2001-2013 Microchip Technology Inc.
FIGURE 10-1: SSP BLOCK DIAGRAM
(SPI MODE)
To enable the serial port, SSP Enable bit, SSPEN
(SSPCON<5>), must be set. To reset or reconfigure
SPI mode, clear bit SSPEN, reinitialize the SSPCON
register and then set bit SSPEN. This configures the
SDI, SDO, SCK and SS
pins as serial port pins. For the
pins to behave as the serial port function, they must
have their data direction bits (in the TRISB register)
appropriately programmed. That is:
• SDI must have TRISB<1> set
• SDO must have TRISB<2> cleared
• SCK (Master mode) must have TRISB<4> cleared
• SCK (Slave mode) must have TRISB<4> set
•SS
must have TRISB<5> set
TABLE 10-1: REGISTERS ASSOCIATED WITH SPI OPERATION
Read Write
Internal
Data Bus
RB1/SDI/SDA
RB2/SDO/
RB5/SS
RB4/SCK/
SSPSR reg
SSPBUF reg
SSPM3:SSPM0
bit 0
Shift
Clock
SS
Control
Enable
Edge
Select
Clock Select
TMR2 Output
T
CY
Prescaler
4, 16, 64
TRISB<4>
2
Edge
Select
2
4
SCL
CCP1
Note 1: When the SPI is in Slave mode
with the SS
pin control enabled
(SSPCON<3:0> = 0100), the SPI module
will reset if the SS
pin is set to VDD.
2: If the SPI is used in Slave mode with
CKE = 1, then the SS pin control must be
enabled.
3: When the SPI is in Slave mode
with the SS
pin control enabled
(SSPCON<3:0> = 0100), the state of the
SS pin can affect the state read back from
the TRISB<2> bit. The peripheral OE
signal from the SSP module into PORTB
controls the state that is read back from
the TRISB<2> bit. If read-modify-write
instructions, such as BSF are performed
on the TRISB register while the SS
pin is
high, this will cause the TRISB<2> bit to
be set, thus disabling the SDO output.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on
all other
Resets
0Bh,8Bh
10Bh,18Bh
INTCON GIE PEIE
TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1
— ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
8Ch PIE1
— ADIE — —SSPIECCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
94h SSPSTAT
SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the SSP in SPI mode.