Datasheet

PIC16F818/819
DS39598F-page 40  2001-2013 Microchip Technology Inc.
FIGURE 5-1: BLOCK DIAGRAM OF
RA0/AN0:RA1/AN1 PINS
FIGURE 5-2: BLOCK DIAGRAM OF
RA3/AN3/V
REF+ PIN
FIGURE 5-3: BLOCK DIAGRAM OF
RA2/AN2/V
REF- PIN
FIGURE 5-4: BLOCK DIAGRAM OF
RA4/AN4/T0CKI PIN
Data
Bus
QD
Q
CK
P
N
WR
PORTA
WR
TRISA
Data Latch
TRIS Latch
RD TRISA
RD PORTA
Analog
V
SS
VDD
I/O pin
QD
Q
CK
Input Mode
DQ
EN
TTL
Input Buffer
VDD
To A/D Module Channel Input
V
SS
Data
Bus
QD
Q
CK
P
N
WR
PORTA
WR
TRISA
Data Latch
TRIS Latch
RD TRISA
RD PORTA
Analog
V
SS
VDD
I/O pin
QD
Q
CK
Input Mode
DQ
EN
VDD
To A/D Module Channel Input
To A/D Module VREF+ Input
V
SS
TTL
Input Buffer
Data
Bus
QD
Q
CK
P
N
WR
PORTA
WR
TRISA
Data Latch
TRIS Latch
RD TRISA
RD PORTA
Analog
V
SS
VDD
I/O pin
QD
Q
CK
Input Mode
DQ
EN
VDD
To A/D Module Channel Input
To A/D Module VREF- Input
V
SS
TTL
Input Buffer
Data
Bus
QD
Q
CK
P
N
WR
PORTA
WR
TRISA
Data Latch
TRIS Latch
RD TRISA
RD PORTA
Analog
V
SS
VDD
I/O pin
QD
Q
CK
Input Mode
DQ
EN
VDD
To A/D Module Channel Input
TMR0 Clock Input
V
SS
Schmitt Trigger
Input Buffer