Datasheet

 2001-2013 Microchip Technology Inc. DS39598F-page 19
PIC16F818/819
2.2.2.4 PIE1 Register
This register contains the individual enable bits for the
peripheral interrupts.
REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS 8Ch)
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
—ADIE— — SSPIE CCP1IE TMR2IE TMR1IE
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’
bit 6 ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
bit 5-4 Unimplemented: Read as ‘0’
bit 3 SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown