Datasheet

© 2008 Microchip Technology Inc. DS41249E-page 95
PIC16F785/HV785
REGISTER 13-3: PWMPH1: PWM PHASE 1 CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
POL C2EN C1EN PH4 PH3 PH2 PH1 PH0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 POL: PH1 Output Polarity bit
1 = PH1 Pin is active-low
0 = PH1 Pin is active-high
bit 6 C2EN: Comparator 2 Enable bit
When COMOD<1:0> =
00
(1)
1 = PH1 is reset when C2OUT goes high
0 = PH1 ignores Comparator 2
When COMOD<1:0> = X1
(1)
1 = Complementary drive terminates when C2OUT goes high
0 = Comparator 2 is ignored
When COMOD<1:0> = 10
(1)
C2EN has no effect
bit 5 C1EN: Comparator 1 Enable bit
When COMOD<1:0> = 00
(1)
1 = PH1 is reset when C1OUT goes high
0 = PH1 ignores Comparator 1
When COMOD<1:0> = X1
(1)
1 = Complementary drive terminates when C1OUT goes high
0 = Comparator 1 is ignored
When COMOD<1:0> = 10
(1)
C1EN has no effect
bit 4-0 PH<4:0>: PWM Phase bits
When COMOD<1:0> = 00
(1)
00000 = PH1 starts 1 pwm_clk period after falling edge of SYNC pulse. All other PH1 delays are
expressed relative to this time.
00001 = PH1 is delayed by 1 pwm_clk pulse
••••• =• • •
11111 = PH1 is delayed by 31 pwm_clk pulses
When COMOD<1:0> =
X1 or 1X
(1)
00000 = Complementary drive starts 1 pwm_clk period after falling edge of SYNC pulse. All other
delays are expressed relative to this time.
00001 = Complementary drive start is delayed by 1 pwm_clk pulse
••••• =• • •
11111 = Complementary drive start is delayed by 31 pwm_clk pulses
Note 1: See PWMCON1 register (Register 13-5).