Datasheet

PIC16F785/HV785
DS41249E-page 92 © 2008 Microchip Technology Inc.
13.5 Active PWM Output Level
The PWM output signal can be made active-high or
active-low by setting or resetting the corresponding
POL bit (see Register 13-3 and Register 13-4). When
POL is ‘1’ the active output state is V
OL. When POL is
‘0’ the active output state is V
OH.
13.6 Auto-Shutdown and Auto-Restart
When the PWM is enabled, the PWM outputs may be
configured for auto-shutdown by setting the PASEN bit
(see Register 13-1). VIL on the RA2/AN2/T0CKI/INT/
C1OUT pin will cause a shutdown event if auto-shut-
down is enabled. An auto-shutdown event immediately
places the PWM outputs in the inactive state (see
Section 13.5 “Active PWM Output Level”) and the
PWM phase and period counters are reset and held to
zero.
The PWMASE bit (see Register 13-2) is set by hard-
ware when a shutdown event occurs. If automatic
restarts are not enabled (PRSEN = 0, see
Register 13-1), PWM operation will not resume until the
PWMASE bit is cleared by firmware after the shutdown
condition clears. The PWMASE bit can not be cleared
as long as the shutdown condition exists. If automatic
restarts are not enabled, the auto-shutdown mode can
be forced by writing a ‘1’ to the PWMASE bit.
If automatic restarts are enabled (PRSEN = 1), the
PWMASE bit is automatically cleared and PWM
operation resumes when the auto-shutdown event
clears (V
IH on the RA2/AN2/T0CKI/INT/C1OUT pin).
FIGURE 13-1: TWO-PHASE PWM SIMPLIFIED BLOCK DIAGRAM
Prescale
PWMPH1<C1EN>
PWMPH1<C2EN>
PWMPH1<POL>
PWMPH1<4:0>
Phase
Counter
FOSC
C1OUT
C2OUT
PWMP<1:0>
PER<4:0>
pwm_clk
5
pwm_count
pha1
÷1,2,4,8
0
1
S
R
(1)
PWMASE
MASTER
M
S
Res
Q
SHUTDOWN
BLANK1
PWMPH2<C1EN>
PWMPH2<C2EN>
PWMPH2<POL>
PWMPH2<4:0>
pha2
S
R
(1)
QSHUTDOWN
BLANK2
PH1EN
PH2EN
PH1EN
PH2EN
PASEN
SHUTDOWN
5
5
5
RB7/SYNC
RC1/AN5/C12IN1-/PH1
RC4/C2OUT/PH2
Note 1: Reset dominant.