Datasheet

PIC16F785/HV785
DS41249E-page 80 © 2008 Microchip Technology Inc.
12.1 A/D Configuration and Operation
There are four registers available to control the
functionality of the A/D module:
1. ANSEL0 (Register 12-1)
2. ANSEL1 (Register 12-2)
3. ADCON0 (Register 12-3)
4. ADCON1 (Register 12-4)
12.1.1 ANALOG PORT PINS
The ANS<11:0> bits, of the ANSEL1 and ANSEL0
Registers, and the TRISA<4,2:0>, TRISB<5:4> and
TRISC<7:6,3:0>> bits control the operation of the A/D
port pins. Set the corresponding TRISx bits to ‘1’ to set
the pin output driver to its high-impedance state. Like-
wise, set the corresponding ANSx bit to disable the dig-
ital input buffer.
12.1.2 CHANNEL SELECTION
There are fourteen analog channels on the PIC16F785/
HV785. The CHS<3:0> bits of the ADCON0 Register
control which channel is connected to the sample and
hold circuit.
12.1.3 VOLTAGE REFERENCE
There are two options for the voltage reference to the
A/D converter: either V
DD is used or an analog voltage
applied to V
REF is used. The VCFG bit of the ADCON0
Register controls the voltage reference selection. If
VCFG is set, then the voltage on the VREF pin is the ref-
erence; otherwise, V
DD is the reference.
12.1.4 CONVERSION CLOCK
The A/D conversion cycle requires 11 TAD. The source
of the conversion clock is software selectable via the
ADCS bits of the ADCON1 Register. There are seven
possible clock options:
•F
OSC/2
•FOSC/4
•F
OSC/8
•F
OSC/16
•FOSC/32
•FOSC/64
•F
RC (dedicated internal oscillator)
For correct conversion, the A/D conversion clock
(1/TAD) must be selected to ensure a minimum TAD of
1.6 μs. Table 12-1 shows a few T
AD calculations for
selected frequencies.
TABLE 12-1: TAD VS. DEVICE OPERATING FREQUENCIES
Note: Analog voltages on any pin that is defined
as a digital input may cause the input
buffer to conduct excess current.
A/D Clock Source (TAD) Device Frequency
Operation ADCS2:ADCS0 20 MHz 5 MHz 4 MHz 1.25 MHz
2 T
OSC 000 100 ns
(2)
400 ns
(2)
500 ns
(2)
1.6 μs
4 TOSC 100 200 ns
(2)
800 ns
(2)
1.0 μs
(2)
3.2 μs
8 TOSC 001 400 ns
(2)
1.6 μs2.0 μs6.4 μs
16 T
OSC 101 800 ns
(2)
3.2 μs4.0 μs 12.8 μs
(3)
32 TOSC 010 1.6 μs6.4 μs 8.0 μs
(3)
25.6 μs
(3)
64 TOSC 110 3.2 μs 12.8 μs
(3)
16.0 μs
(3)
51.2 μs
(3)
A/D RC x11 2-6 μs
(1), (4)
2-6 μs
(1), (4)
2-6 μs
(1), (4)
2-6 μs
(1), (4)
Legend: Shaded cells are outside of recommended range.
Note 1: The A/D RC source has a typical TAD time of 4 μs for VDD > 3.0V.
2: These values violate the minimum required T
AD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the
conversion will be performed during Sleep.