Datasheet

PIC16F785/HV785
DS41249E-page 74 © 2008 Microchip Technology Inc.
10.2.1 VR STABILIZATION PERIOD
When the Voltage Reference module is enabled, it will
require some time for the reference and its amplifier
circuits to stabilize. The user program must include a
small delay routine to allow the module to settle. See
Section 19.0 “Electrical Specifications” for the
minimum delay requirement.
FIGURE 10-2: VR REFERENCE BLOCK DIAGRAM
TABLE 10-1: REGISTERS ASSOCIATED WITH COMPARATOR AND VOLTAGE REFERENCE
MODULES
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on all
other Resets
ANSEL0 ANS7 ANS6 ANS5 ANS4
ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111
CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0 0000 0000 0000 0000
CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0 0000 0000 0000 0000
CM2CON1 MC1OUT MC2OUT
— — — — T1GSS C2SYNC 00-- --10 00-- --10
PIE1
EEIE ADIE CCP1IE C2IE C1IE OSFIE TMR2IE TMR1IE 0000 ---0 0000 ---0
PIR1
EEIF ADIF CCP1IF C2IF C1IF OSFIF TMR2IF TMR1IF 0000 ---0 0000 ---0
PORTA
— — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu
PORTC
RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
REFCON
— — BGST VRBB VREN VROE CVROE — --00 000- --00 000-
TRISA
— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
VRCON C1VREN C2VREN VRR
— VR3 VR2 VR1 VR0 000- 0000 000- 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for comparator.
RA1/AN1/C12IN0-/VREF
VREN
Voltage
Reference
EN
RDY
To CV
REF MUX
BGST
VR
1
0
1X
Analog
Buffer
CVREF
VRBB
(1)
VROUT
CVROE
(CVROE + (VREN*VROE))
1
0
VRIN
Note 1: Buffered output requires VRIN = (VDD - 1.4)V.
2: VREN is fixed high for PIC16HV785 device.