Datasheet

© 2008 Microchip Technology Inc. DS41249E-page 69
PIC16F785/HV785
9.2 Comparator Outputs
The comparator outputs are read through the
CM1CON0, COM2CON0 or CM2CON1 registers.
CM1CON0 and CM2CON0 each contain the individual
comparator output of Comparator 1 and Comparator 2,
respectively. CM2CON2 contains a mirror copy of both
comparator outputs facilitating a simultaneous read of
both comparators. These bits are read-only. The
comparator outputs may also be directly output to the
RA2/AN2/T0CKI/INT/C1OUT and RC4/C2OUT/PH2
I/O pins. When enabled, multiplexers in the output path
of the RA2 and RC4 pins will switch and the output of
each pin will be the unsynchronized output of the com-
parator. The uncertainty of each of the comparators is
related to the input offset voltage and the response time
given in the specifications. Figure 9-1 and Figure 9-2
show the output block diagrams for Comparators 1 and
2, respectively.
The TRIS bits will still function as an output enable/
disable for the RA2/AN2/T0CKI/INT/C1OUT and RC4/
C2OUT/PH2 pins while in this mode.
The polarity of the comparator outputs can be changed
using the C1POL and C2POL bits of the CMxCON0
Register.
Timer1 gate source can be configured to use the T1G
pin or Comparator 2 output as selected by the T1GSS
bit of the CM2CON1 Register. The Timer1 gate feature
can be used to time the duration or interval of analog
events. The output of Comparator 2 can also be syn-
chronized with Timer1 by setting the C2SYNC bit of the
CM2CON1 Register. When enabled, the output of
Comparator 2 is latched on the falling edge of the
Timer1 clock source. If a prescaler is used with Timer1,
Comparator 2 is latched after the prescaler. To prevent
a race condition, the Comparator 2 output is latched on
the falling edge of the Timer1 clock source and Timer1
increments on the rising edge of its clock source. See
the Comparator 2 Block Diagram (Figure 9-2) and the
Timer1 Block Diagram (Figure 6-1) for more
information.
It is recommended to synchronize Comparator 2 with
Timer1 by setting the C2SYNC bit when Comparator 2
is used as the Timer1 gate source. This ensures Timer1
does not miss an increment if Comparator 2 changes
during an increment.
9.3 Comparator Interrupts
The comparator interrupt flags are set whenever there
is a change in the output value of its respective compar-
ator. Software will need to maintain information about
the status of the output bits, as read from
CM2CON0<7:6>, to determine the actual change that
has occurred. The CxIF bits, PIR1<4:3>, are the
Comparator Interrupt Flags. Each comparator interrupt
bit must be reset in software by clearing it to ‘0’. Since
it is also possible to write a ‘1’ to this register, a
simulated interrupt may be initiated.
The CxIE bits of the PIE1 Register and the PEIE bit of
the INTCON Register must be set to enable the inter-
rupts. In addition, the GIE bit must also be set. If any of
these bits are cleared, the interrupt is not enabled,
though the CxIF bits will still be set if an interrupt con-
dition occurs.
The comparator interrupt of the PIC16F785/HV785
differs from previous designs in that the interrupt flag is
set by the mismatch edge and not the mismatch level.
This means that the interrupt flag can be reset without
the additional step of reading or writing the CMxCON0
register to clear the mismatch registers. When the
mismatch registers are not cleared, an interrupt will not
occur when the comparator output returns to the
previous state. When the mismatch registers are
cleared, an interrupt will occur when the comparator
returns to the previous state.
9.4 Effects of Reset
A Reset forces all registers to their Reset state. This
disables both comparators.
Note 1: If a change in the CMxCON0 register
(CxOUT) should occur when a read
operation is being executed (start of the
Q2 cycle), then the CxIF of the PIR1 Reg-
ister interrupt flag may not get set.
2: When either comparator is first enabled,
bias circuitry in the Comparator module
may cause an invalid output from the
comparator until the bias circuitry is sta-
ble. Allow about 1 μs for bias settling then
clear the mismatch condition and inter-
rupt flags before enabling comparator
interrupts.