Datasheet

PIC16F785/HV785

9.1.2.2 Control Register CM2CON1

Comparator C2 has one additional feature: its output

can be synchronized to the Timer1 clock input. Setting

C2SYNC of the CM2CON1 Register synchronizes the

output of Comparator 2 to the falling edge of the Timer1

clock input (see Figure 9-2 and Register 9-3).

The CM2CON1 register also contains mirror copies of

both comparator outputs, MC1OUT and MC2OUT of

the CM2CON1 Register. The ability to read both out-

puts simultaneously from a single register eliminates

the timing skew of reading separate registers.

Note: Obtaining the status of C1OUT or C2OUT

by reading CM2CON1 does not affect the

comparator interrupt mismatch registers.

R-0 R-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0

MC1OUT MC2OUT — — — — T1GSS C2SYNC

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 MC1OUT: Mirror Copy of C1OUT bit (CM1CON0<6>)

bit 6 MC2OUT: Mirror Copy of C2OUT bit (CM2CON0<6>)

bit 5-2 Unimplemented: Read as ‘0’

bit 1 T1GSS: Timer1 Gate Source Select bit

1 = Timer1 gate source is RA4/AN3/T1G/OSC2/CLKOUT

0 = Timer1 gate source is SYNCC2OUT.

bit 0 C2SYNC: C2 Output Synchronous Mode bit

1 = C2 output is synchronous to falling edge of TMR1 clock

0 = C2 output is asynchronous