Datasheet

PIC16F785/HV785
DS41249E-page 66 © 2008 Microchip Technology Inc.
9.1.2 COMPARATOR C2 CONTROL
REGISTERS
The CM2CON0 register is a functional copy of the
CM1CON0 register described in Section 9.1.1 “Com-
parator C1 Control Register”. A second control regis-
ter, CM2CON1, is also present for control of an
additional synchronizing feature, as well as mirrors of
both comparator outputs.
9.1.2.1 Control Register CM2CON0
The CM2CON0 register, shown in Register 9-2,
contains the control and Status bits for Comparator C2.
Setting C2ON of the CM2CON0 Register enables
Comparator C2 for operation.
Bits C2CH<1:0> of the CM2CON0 Register select the
comparator input from the four analog pins, AN<7:5,1>.
C2R of the CM2CON0 Register selects the reference
to be used with the comparator. Setting C2R of the
CM2CON0 Register selects the C2V
REF output of the
comparator voltage reference module as the reference
voltage for the comparator. Clearing C2R selects the
C2IN+ input on the RC0/AN4/C2IN+ pin.
The output of the comparator is available internally via
the C2OUT bit of the CM2CON0 Register. To make the
output available for an external connection, the C2OE
bit of the CM2CON0 Register must be set.
The comparator output, C2OUT, can be inverted by
setting the C2POL bit of the CM2CON0 Register.
Clearing C2POL results in a non-inverted output.
A complete table showing the output state versus input
conditions and the polarity bit is shown in Table 9-2.
TABLE 9-2: C2 OUTPUT STATE VERSUS
INPUT CONDITIONS
C2SP of the CM2CON0 Register configures the speed
of the comparator. When C2SP is set, the comparator
operates at its normal speed. Clearing C2SP operates
the comparator in low-power mode.
FIGURE 9-2: COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM
Note: To use AN<7:5,1> as analog inputs, the
appropriate bits must be programmed to 1
in the ANSEL0 register.
Input Condition C2POL C2OUT
C2VN > C2VP 00
C2VN < C2VP 01
C2VN > C2VP 11
C2VN < C2VP 10
Note 1: The internal output of the comparator is
latched at the end of each instruction
cycle. External outputs are not latched.
2: The C2 interrupt will operate correctly
with C2OE set or cleared. An external
output is not required for the C2 interrupt.
3: For C2 output on RC4/C2OUT/PH2:
(C2OE = 1) and (C2ON = 1) and
(TRISA<4> = 0).
MUX
C2POL
C2OUT
To PWM Logic
0
1
2
3
C2CH<1:0>
2
0
1
C2R
From TMR1
Clock
Note 1: When C2ON = 0, the C2 comparator will produce a ‘0’ output to the XOR Gate.
2: Timer1 gate control (see Figure 6-1).
3: Output shown for reference only. For more detail, see Figure 4-13.
C20E
C2VREF
MUX
DQ
EN
DQ
EN
CL
DQ
RD_CM2CON0
Q3*RD_CM2CON0
Q1
Set C2IF
To
NRESET
C2VN
C2VP
RC4/C2OUT/PH2
(3)
RC0/AN4/C2IN+
RA1/AN1/C12IN0-/V
REF/ICSPCLK
RC1/AN5/C12IN1-/PH1
RC2/AN6/C12IN2-/OP2
RC3/AN7/C12IN3-/OP1
0
1
C2SYNC
SYNCC2OUT
(2)
C2POL
Data Bus
MUX
C2
C2ON
(1)
C2SP