Datasheet

© 2008 Microchip Technology Inc. DS41249E-page 63
PIC16F785/HV785
9.0 COMPARATOR MODULE
The Comparator module has two separate voltage
comparators: Comparator 1 (C1) and Comparator 2
(C2).
Each comparator offers the following list of features:
• Control and Configuration register
• Comparator output available externally
• Programmable output polarity
• Interrupt-on-change flags
• Wake-up from Sleep
• Configurable as feedback input to the PWM
• Programmable four input multiplexer
• Programmable two input reference selections
• Programmable speed/power
• Output synchronization to Timer1 clock input
(Comparator C2 only)
9.1 Control Registers
Both comparators have separate control and Configu-
ration registers: CM1CON0 for C1 and CM2CON0 for
C2. In addition, Comparator C2 has a second control
register, CM2CON1, for synchronization control and
simultaneous reading of both comparator outputs.
9.1.1 COMPARATOR C1 CONTROL
REGISTER
The CM1CON0 register (shown in Register 9-1)
contains the control and Status bits for the following:
• Comparator enable
• Comparator input selection
• Comparator reference selection
• Output mode
• Comparator speed
Setting C1ON (CM1CON0<7>) enables Comparator
C1 for operation.
Bits C1CH<1:0> of the CM1CON0 Register select the
comparator input from the four analog pins AN<7:5,1>.
Setting C1R of the CM1CON0 Register selects the
C1V
REF output of the comparator voltage reference
module as the reference voltage for the comparator.
Clearing C1R selects the C1IN+ input on the RA0/AN0/
C1IN+/ICSPDAT pin.
The output of the comparator is available internally via
the C1OUT flag of the CM1CON0 Register. To make
the output available for an external connection, the
C1OE bit of the CM1CON0 Register must be set.
The polarity of the comparator output can be inverted
by setting the C1POL bit of the CM1CON0 Register.
Clearing C1POL results in a non-inverted output.
A complete table showing the output state versus input
conditions and the polarity bit is shown in Table 9-1.
TABLE 9-1: C1 OUTPUT STATE VERSUS
INPUT CONDITIONS
C1SP of the CM1CON0 Register configures the speed
of the comparator. When C1SP is set, the comparator
operates at its normal speed. Clearing C1SP operates
the comparator in a slower, low-power mode.
Note: To use AN<7:5,1> as analog inputs the
appropriate bits must be programmed to
‘1’ in the ANSEL0 register.
Input Condition C1POL C1OUT
C1VN > C1VP 00
C1VN < C1VP 01
C1VN > C1VP 11
C1VN < C1VP 10
Note 1: The internal output of the comparator is
latched at the end of each instruction
cycle. External outputs are not latched.
2: The C1 interrupt will operate correctly
with C1OE set or cleared.
3: To output C1 on RA2/AN2/T0CKI/INT/
C1OUT:(C1OE = 1) and (C1ON = 1) and
(TRISA<2> = 0).