Datasheet
PIC16F785/HV785
DS41249E-page 62 © 2008 Microchip Technology Inc.
8.3.3 OPERATION IN SLEEP MODE
In Sleep mode, all clock sources are disabled. Timer2
will not increment and the state of the module will not
change. If the RC5/CCP1 pin is driving a value, it will
continue to drive that value. When the device wakes
up, it will continue from this state.
8.3.3.1 OPERATION WITH FAIL-SAFE
CLOCK MONITOR
If the Fail-Safe Clock Monitor is enabled, a clock failure
will force the CCP to be clocked from the internal
oscillator clock source, which may have a different
clock frequency than the primary clock.
See Section 3.0 “Clock Sources” for additional
details.
8.3.4 EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
8.3.5 SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Configure the PWM pin (RC5/CCP1) as an input
by setting the TRISC<5> bit.
2. Set the PWM period by loading the PR2 register.
3. Configure the CCP module for the PWM mode
by loading the CCP1CON register with the
appropriate values.
4. Set the PWM duty cycle by loading the CCPR1L
register and CCP1CON<5:4> bits.
5. Configure and start TMR2:
• Clear the TMR2 interrupt flag bit by clearing
the TMR2IF bit of the PIR1 Register.
• Set the TMR2 prescale value by loading the
T2CKPS bits of the T2CON Register.
• Enable Timer2 by setting the TMR2ON bit of
the T2CON Register.
6. Enable PWM output after a new PWM cycle has
started:
• Wait until TMR2 overflows (TMR2IF bit is
set).
• Enable the RC5/CCP1 pin output by clearing
the TRISC<5> bit.
TABLE 8-4: REGISTERS ASSOCIATED WITH CCP AND TIMER2
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on all
other Resets
CCP1CON
— — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx uuuu uuuu
CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx uuuu uuuu
INTCON GIE PEIE
T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000
PIE1
EEIE ADIE CCP1IE C2IE C1IE OSFIE TMR2IE TMR1IE 0000 0000 0000 0000
PIR1
EEIF ADIF CCP1IF C2IF C1IF OSFIF TMR2IF TMR1IF 0000 0000 0000 0000
PR2 Timer2 Module Period Register 1111 1111 1111 1111
T2CON
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
TMR2 Timer2 Module Register 0000 0000 0000 0000
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111
Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the CCP or Timer2 modules.