Datasheet

© 2008 Microchip Technology Inc. DS41249E-page 61
PIC16F785/HV785
8.3.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the DC1B<1:0> bits of the
CCP1CON register. Up to 10 bits of resolution is avail-
able. The CCPR1L contains the eight MSbs and the
DC1B<1:0> contains the two LSbs. In PWM mode,
CCPR1H is a read-only register.
Equation 8-2 is used to calculate the PWM duty cycle
in time.
EQUATION 8-2: PWM DUTY CYCLE
CCPR1L and DC1B<1:0> can be written to at any time,
but the duty cycle value is not latched into CCPR1H
until after a match between PR2 and TMR2 occurs
(i.e. the period is complete). In PWM mode, CCPR1H
is a read-only register.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
Because of the buffering, the module waits until the
timer resets, instead of starting immediately. This
means that enhanced PWM waveforms do not exactly
match the standard PWM waveforms, but are instead
offset by one full instruction cycle (4 T
OSC).
When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the RC5/CCP1 pin is cleared.
The maximum PWM resolution is a function of PR2 as
shown by Equation 8-3.
EQUATION 8-3: PWM RESOLUTION
TABLE 8-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (F
OSC = 20 MHz)
PWM duty cycle CCPR1L:CCP1CON<5:4>() •=
T
OSC • (TMR2 prescale value)
Note: If the PWM duty cycle value is longer than
the PWM period, the assigned PWM pin(s)
will remain unchanged.
Resolution
4PR2 1+()[]log
2()log
------------------------------------------ bits=
PWM Frequency 1.22 kHz
(1)
4.88 kHz
(1)
19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescale (1, 4, 16) 16 4 1 1 1 1
PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17
Maximum Resolution (bits) 10 10 10 8 7 6.6
Note 1: Changing duty cycle will cause a glitch.