Datasheet

PIC16F785/HV785
DS41249E-page 60 © 2008 Microchip Technology Inc.
8.3 CCP PWM Mode
In Pulse Width Modulation (PWM) mode, the CCP
module produces up to a 10-bit resolution PWM output
on the RC5/CCP1 pin. Since the RC5/CCP1 pin is
multiplexed with the PORTC data latch, the TRISC<5>
must be cleared to make the RC5/CCP1 pin an output.
Figure 8-3 shows a simplified block diagram of PWM
operation.
For a step by step procedure on how to set up the CCP
module for PWM operation, see Section 8.3.5 “Setup
for PWM Operation”.
FIGURE 8-3: SIMPLIFIED PWM BLOCK
DIAGRAM
The PWM output (Figure 8-4) has a time base
(period) and a time that the output stays high (duty
cycle). The frequency of the PWM is the inverse of
the period (1/period).
FIGURE 8-4: CCP PWM OUTPUT
8.3.1 PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
formula of Equation 8-1.
EQUATION 8-1: PWM PERIOD
PWM frequency is defined as 1/[PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
•TMR2 is cleared
• The RC5/CCP1 pin is set. (exception: if PWM
duty cycle = 0%, the pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
Note: Clearing the CCP1CON register will force
the PWM output latch to the default
inactive levels. This is not the PORTC I/O
data latch.
CCPR1L
CCPR1H (Slave)
Comparator
TMR2
PR2
(1)
RQ
S
Duty Cycle Registers
CCP1CON<5:4>
Clear Timer2,
toggle PWM pin and
latch duty cycle
Note 1: The 8-bit timer TMR2 register is concate-
nated with the 2-bit internal Q clock, or 2 bits
of the prescaler, to create the 10-bit time
base.
TRISC<5>
RC5/CCP1
Comparator
Period
Duty Cycle
TMR2 = 0
TMR2 = Duty Cycle
TMR2 = PR2
Note: The Timer2 postscaler (see Section 7.1
“Timer2 Operation”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
PWM period PR2()1+[]4TOSC •••=
(TMR2 prescale value)