Datasheet
© 2008 Microchip Technology Inc. DS41249E-page 59
PIC16F785/HV785
8.2.1 CCP1 PIN CONFIGURATION
The user must configure the RC5/CCP1 pin as an
output by clearing the TRISC<5> bit.
8.2.2 TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
8.2.3 SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen
(CCP1M<3:0> = 1010), the RC5/CCP1 pin is not
affected. The CCP1IF bit of the PIR1 Register is set,
causing a CCP interrupt (if enabled). See Register 8-1.
8.2.4 SPECIAL EVENT TRIGGER
In this mode (CCP1M<3:0> = 1011), an internal
hardware trigger is generated, which may be used to
initiate an action. See Register 8-1.
The special event trigger output of the CCP occurs
immediately upon a match between the TMR1H,
TMR1L register pair and CCPR1H, CCPR1L register
pair. The TMR1H, TMR1L register pair is not reset until
the next rising edge of the TMR1 clock. This allows the
CCPR1H, CCPR1L register pair to effectively provide a
16-bit programmable period register for Timer1. The
special event trigger output also starts an A/D
conversion provided that the A/D module is enabled.
TABLE 8-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Note: Clearing the CCP1CON register will force
the RC5/CCP1 compare output latch to
the default low level. This is not the
PORTC I/O data latch.
Note 1: The special event trigger from the CCP
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
2: Removing the match condition by chang-
ing the contents of the CCPR1H and
CCPR1L register pair between the clock
edge that generates the special event
trigger and the clock edge that generates
the TMR1 Reset, will preclude the Reset
from occurring.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on all
other Resets
CCP1CON
— — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx uuuu uuuu
CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx uuuu uuuu
CM2CON1
MC1OUT MC2OUT — — — —T1GSSC2SYNC 00-- --10 00-- --10
INTCON GIE PEIE
T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000
PIE1
EEIE ADIE CCP1IE C2IE C1IE OSFIE TMR2IE TMR1IE 0000 0000 0000 0000
PIR1
EEIF ADIF CCP1IF C2IF C1IF OSFIF TMR2IF TMR1IF 0000 0000 0000 0000
T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON 0000 0000 uuuu uuuu
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111
Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture, Compare or Timer1
module.