Datasheet

PIC16F785/HV785

7.2 Timer2 Interrupt

The Timer2 module has an 8-bit period register, PR2.

Timer2 increments from 00h until it matches PR2 and

then resets to 00h on the next increment cycle. PR2 is

a readable and writable register. The PR2 register is

initialized to FFh upon Reset.

FIGURE 7-1: TIMER2 BLOCK DIAGRAM

TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER2

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Value on all

other Resets

INTCON GIE PEIE

T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000

PIE1

EEIE ADIE CCP1IE C2IE C1IE OSFIE TMR2IE TMR1IE 0000 0000 0000 0000

PIR1

EEIF ADIF CCP1IF C2IF C1IF OSFIF TMR2IF TMR1IF 0000 0000 0000 0000

PR2 Timer2 Module Period register 1111 1111 1111 1111

T2CON

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

TMR2 Holding Register for the 8-bit TMR2 Register 0000 0000 0000 0000

Legend: – x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.

Comparator

TMR2

Sets Flag

TMR2

Output

Reset

Postscaler

Prescaler

PR2

OSC/4

1:1 to 1:16

1:1, 1:4, 1:16

bit TMR2IF

TOUTPS<3:0>

T2CKPS<1:0>