Datasheet

PIC16F785/HV785
DS41249E-page 54 © 2008 Microchip Technology Inc.
6.5 Timer1 Operation in
Asynchronous Counter Mode
If control bit T1SYNC of the T1CON Register is set, the
external clock input is not synchronized. The timer con-
tinues to increment asynchronous to the internal phase
clocks. The timer will continue to run during Sleep and
can generate an interrupt on overflow, which will wake-
up the processor. However, special precautions in
software are needed to read/write the timer
(Section 6.5.1 “Reading and Writing Timer1 in
Asynchronous Counter Mode”).
6.5.1 READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write conten-
tion may occur by writing to the timer registers, while
the register is incrementing. This may produce an
unpredictable value in the timer register.
6.6 Timer1 Oscillator
A crystal oscillator circuit is built-in between pins OSC1
(input) and OSC2 (amplifier output). It is enabled by
setting control bit T1OSCEN of the T1CON Register.
The oscillator is a low power oscillator rated for 32.768
kHz. It will continue to run during Sleep. It is primarily
intended for a 32.768 kHz tuning fork crystal.
The Timer1 oscillator is shared with the system LP
oscillator. Thus, Timer1 can use this mode only when
the primary system clock is also the LP oscillator or is
derived from the internal oscillator. As with the system
LP oscillator, the user must provide a software time
delay to ensure proper oscillator start-up.
Sleep mode will not disable the system clock when the
system clock and Timer1 share the LP oscillator.
TRISA<5> and TRISA<4> bits are set when the Timer1
oscillator is enabled. RA5 and RA4 read as ‘0’ and
TRISA<5> and TRISA<4> bits read as ‘1’.
6.7 Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in
Asynchronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To setup the timer to wake the device:
• Timer1 of the T1CON Register must be on
• TMR1IE bit of the PIE1 Register must be set
• PEIE bit of the INTCON Register must be set
The device will wake-up on an overflow. If the GIE bit of
the INTCON Register is set, the device will wake-up
and jump to the Interrupt Service Routine (0004h) on
an overflow. If the GIE bit is clear, execution will con-
tinue with the next instruction.
TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER1
Note: The ANSEL0 (91h) register must be initial-
ized to configure an analog channel as a
digital input. Pins configured as analog
inputs will read ‘0’.
Note: The oscillator requires a start-up and
stabilization time before use. Thus,
T1OSCEN should be set and a suitable
delay observed prior to enabling Timer1.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on all
other Resets
ANSEL0
ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111
CM2CON1
MC1OUT MC2OUT — — — —T1GSSC2SYNC 00-- --10 00-- --10
INTCON GIE PEIE
T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000
PIE1
EEIE ADIE CCP1IE C2IE C1IE OSFIE TMR2IE TMR1IE 0000 0000 0000 0000
PIR1
EEIF ADIF CCP1IF C2IF C1IF OSFIF TMR2IF TMR1IF 0000 0000 0000 0000
T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON 0000 0000 uuuu uuuu
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
Legend: – x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.