Datasheet

PIC16F785/HV785
DS41249E-page 52 © 2008 Microchip Technology Inc.
6.1 Timer1 Modes of Operation
Timer1 can operate in one of three modes:
• 16-bit Timer with prescaler
• 16-bit Synchronous counter
• 16-bit Asynchronous counter
In Timer mode, Timer1 is incremented on every instruc-
tion cycle. In Counter mode, Timer1 is incremented on
the rising edge of the external clock input T1CKI. In
addition, the Counter mode clock can be synchronized
to the microcontroller system clock or run
asynchronously.
In Counter and Timer modules, the counter/timer clock
can be gated by the Timer1 gate, which can be
selected as either the T1G pin or Comparator 2 output.
If an external clock oscillator is needed (and the
microcontroller is using the LP oscillator or INTOSC
without CLKOUT), Timer1 can use the LP oscillator as
a clock source.
6.2 Timer1 Interrupt
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt flag bit of the PIR1 Register
is set. To enable the interrupt on rollover, you must set
these bits:
• Timer1 Interrupt Enable bit of the PIE1 Register
• PEIE bit of the INTCON Register
• GIE bit of the INTCON Register
The interrupt is cleared by clearing the TMR1IF in the
Interrupt Service Routine.
6.3 Timer1 Prescaler
Timer1 has four prescaler options allowing 1, 2, 4 or 8
divisions of the clock input. The T1CKPS bits, of the
T1CON Register, control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write
to TMR1H or TMR1L.
6.4 Timer1 Gate
Timer1 gate source is software configurable to be T1G
pin or the output of Comparator 2. This allows the
device to directly time external events using T1G or
analog events using Comparator 2. See CM2CON1
(Register 9-3) for selecting the Timer1 gate source.
This feature can simplify the software for a Delta-Sigma
A/D Converter and many other applications. For more
information on Delta-Sigma A/D Converters, see the
Microchip web site (www.microchip.com).
Timer1 gate can be inverted using the T1GINV bit of
the T1CON Register, whether it originates from the
T1G pin or Comparator 2 output. This configures
Timer1 to measure either the active high or active low
time between events.
FIGURE 6-2: TIMER1 INCREMENTING EDGE
Note: In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge after any one or
more of the following conditions.
• Timer1 enabled after POR Reset
• Write to TMR1H or TMR1L
• Timer1 is disabled (TMR1ON = 0)
when T1CKI is high then Timer1 is
enabled (TMR1ON = 1) when T1CKI
is low. See Figure 6-2.
Note: The TMR1H:TMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.
Note: TMR1GE bit, of the T1CON Register, must
be set to use either T1G or C2OUT as the
Timer1 gate source. See Register 9-3 for
more information on selecting the Timer1
gate source.
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1: Arrows indicate counter increments.
2: See note box in Section 6.1 “Timer1 Modes of Operation”.