Datasheet

© 2008 Microchip Technology Inc. DS41249E-page 51
PIC16F785/HV785
6.0 TIMER1 MODULE WITH GATE
CONTROL
The Timer1 module is the 16-bit counter of the
PIC16F785/HV785. Figure 6-1 shows the basic block
diagram of the Timer1 module. Timer1 has the follow-
ing features:
• 16-bit timer/counter (TMR1H:TMR1L)
• Readable and writable
• Internal or external clock selection
• Synchronous or asynchronous operation
• Interrupt on overflow from FFFFh to 0000h
• Wake-up upon overflow (Asynchronous mode)
• Optional external enable input:
- Selectable gate source; T1G or C2 output
(T1GSS)
- Selectable gate polarity (T1GINV)
• Optional LP oscillator
The Timer1 Control register (T1CON), shown in
Register 6-1, is used to enable/disable Timer1 and
select the various features of the Timer1 module.
FIGURE 6-1: TIMER1 ON THE PIC16F785/HV785 BLOCK DIAGRAM
TMR1H
TMR1L
Oscillator
T1SYNC
TMR1CS
T1CKPS<1:0>
Sleep input
F
OSC/4
Internal
Clock
Prescaler
1, 2, 4, 8
Synchronize
det
1
0
0
1
Synchronized
clock input
2
Set flag bit
TMR1IF on
Overflow
TMR1
(1)
TMR1ON
TMR1GE
TMR1ON
TMR1GE
INTOSC
T1OSCEN
Without CLKOUT
*
1
0
SYNCC2OUT
(2)
T1GSS
T1GINV
To C2 Comparator Module
TMR1 Clock
* ST Buffer is low power type when using LP OSC, or high-speed type when using T1CKI.
Note 1: Timer1 increments on the rising edge.
2: SYNCC2OUT is the synchronized output from Comparator 2 (See Figure 9-2 on 66).
RA5/T1CKI/OSC1/CLKIN
RA4/AN3/T1G/OSC2/CLKOUT
LP
Sleep
DQ
EN