Datasheet

PIC16F785/HV785
DS41249E-page 50 © 2008 Microchip Technology Inc.
5.3 Using Timer0 with an External
Clock
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI, with the internal phase clocks, is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2T
OSC (and
a small RC delay of 20 ns) and low for at least 2T
OSC
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
5.4 Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer. For simplicity, this counter will be referred to as
“prescaler” throughout this Data Sheet. The prescaler
assignment is controlled in software by the control bit
PSA of the OPTION Register. Clearing the PSA bit will
assign the prescaler to Timer0. Prescale values are
selectable via the PS<2:0> bits of the OPTION Regis-
ter.
The prescaler is not readable or writable. When
assigned to the Timer0 module, all instructions writing
to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1,x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer.
5.4.1 SWITCHING PRESCALER
ASSIGNMENT
The prescaler assignment is fully under software
control (i.e., it can be changed “on the fly” during
program execution). To avoid an unintended device
Reset, the following instruction sequence (Example 5-
1 and Example 5-2) must be executed when changing
the prescaler assignment between Timer0 and WDT.
EXAMPLE 5-1: CHANGING PRESCALER
(TIMER0→WDT)
To change prescaler from the WDT to the TMR0
module, use the sequence shown in Example 5-2. This
precaution must be taken even if the WDT is disabled.
EXAMPLE 5-2: CHANGING PRESCALER
(WDT→TIMER0)
TABLE 5-1: REGISTERS ASSOCIATED WITH TIMER0
BCF STATUS,RP0 ;Bank 0
BCF STATUS,RP1 ;
CLRWDT ;Clear WDT
CLRF TMR0 ;Clear TMR0 and
; prescaler
BSF STATUS,RP0 ;Bank 1
MOVLW b’00101111’ ;Required if desired
MOVWF OPTION_REG ; PS2:PS0 is
CLRWDT ; 000 or 001
;
MOVLW b’00101xxx’ ;Set postscaler to
MOVWF OPTION_REG ; desired WDT rate
BCF STATUS,RP0 ;Bank 0
CLRWDT ;Clear WDT and
; prescaler
BSF STATUS,RP0 ;Bank 1
BCF STATUS,RP1 ;
MOVLW b’xxxx0xxx’ ;Select TMR0,
; prescale, and
; clock source
MOVWF OPTION_REG ;
BCF STATUS,RP0 ;Bank 0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on all
other Resets
ANSEL0
ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111
INTCON GIE PEIE T0IE
INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000
OPTION_REG
RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu
TRISA
— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module.