Datasheet

© 2008 Microchip Technology Inc. DS41249E-page 49
PIC16F785/HV785
5.0 TIMER0 MODULE
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Figure 5-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
5.1 Timer0 Operation
Timer mode is selected by clearing the T0CS bit of the
OPTION Register. In Timer mode, the Timer0 module
will increment every instruction cycle (without pres-
caler). If TMR0 is written, the increment is inhibited for
the following two instruction cycles. The user can work
around this by writing an adjusted value to the TMR0
register.
Counter mode is selected by setting the T0CS bit of the
OPTION Register. In this mode, the Timer0 module will
increment either on every rising or falling edge of pin
RA2/AN2/T0CKI/INT/C1OUT. The incrementing edge
is determined by the source edge (T0SE) control bit of
the OPTION Register. Clearing the T0SE bit selects the
rising edge.
5.2 Timer0 Interrupt
A Timer0 interrupt is generated when the TMR0
register timer/counter overflows from FFh to 00h. This
overflow sets the T0IF bit of the INTCON Register. The
interrupt can be masked by clearing the T0IE bit of the
INTCON Register. The T0IF bit must be cleared in soft-
ware by the Timer0 module Interrupt Service Routine
before re-enabling this interrupt. The Timer0 interrupt
cannot wake the processor from Sleep since the timer
is shut-off during Sleep.
FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Note 1: Counter mode has specific external clock
requirements.
2: The ANSEL0 (91h) register must be ini-
tialized to configure an analog channel as
a digital input. Pins configured as analog
inputs will read ‘0’.
T0SE
(1)
CLKOUT
TMR0
Watchdog
Timer
WDT
Time-out
PS<0:2>
(1)
WDTE
Data Bus
Set Flag bit T0IF
on Overflow
T0CS
(1)
Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION_REG (see Register 2.2.2.3).
2: WDTPS<3:0> are bits in the WDTCON register (see Register 15-2).
0
1
0
1
0
1
SYNC 2
Cycles
8
8
8-bit
Prescaler
0
1
(= FOSC/4)
PSA
(1)
PSA
(1)
PSA
(1)
16-bit
Prescaler
16
WDTPS<3:0>
(2)
31 kHz
INTRC
SWDTEN
RA2/AN2/T0CKI/INT/C1OUT