Datasheet

PIC16F785/HV785
DS41249E-page 40 © 2008 Microchip Technology Inc.
4.2.3.5 RA4/AN3/T1G/OSC2/CLKOUT
Figure 4-5 shows the diagram for this pin. The RA4 pin
is configurable to function as one of the following:
General purpose I/O
Analog input for the A/D
TMR1 gate input
Crystal/resonator connection
Clock output
FIGURE 4-5: BLOCK DIAGRAM OF RA4
4.2.3.6 RA5/T1CKI/OSC1/CLKIN
Figure 4-6 shows the diagram for this pin. The RA5 pin
is configurable to function as one of the following:
General purpose I/O
TMR1 clock input
Crystal/resonator connection
Clock input
FIGURE 4-6: BLOCK DIAGRAM OF RA5
I/O pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
Weak
Data Bus
WR
WPUA
RD
WPUA
RD
PORTA
WR
PORTA
WR
TRISA
RD
TRISA
WR
IOCA
RD
IOCA
FOSC/4
To A/D Converter
Oscillator
Circuit
OSC1
CLKOUT
0
1
Enable
ANS3
RAPU
To T1 G
INTOSC/
RC/EC
(2)
CLK
(1)
Modes
CLKOUT
Enable
Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT
Enable.
2: With CLKOUT option.
Interrupt-on-
CHANGE
ANS3
D
EN
Q
D
EN
Q
D
EN
Q
Q1
Q3
RD PORTA
S
I/O pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
Weak
Data Bus
WR
WPUA
RD
WPUA
RD
PORTA
WR
PORTA
WR
TRISA
RD
TRISA
WR
IOCA
RD
IOCA
To TMR1 or CLKGEN
INTOSC
Mode
INTOSC
Mode
RAPU
OSC2
(2)
Note 1: CLK modes are XT, HS, LP and LPTMR1.
2: When using Timer1 with LP oscillator, the
Schmitt Trigger is bypassed.
CLK modes
(1)
Interrupt-on-
Change
Oscillator
Circuit
D
EN
Q
D
EN
Q
D
EN
Q
Q1
Q3
RD PORTA
S