Datasheet
© 2008 Microchip Technology Inc. DS41249E-page 39
PIC16F785/HV785
4.2.3.3 RA2/AN2/T0CKI/INT/C1OUT
Figure 4-3 shows the diagram for this pin. The RA2 pin
is configurable to function as one of the following:
• General purpose I/O
• Analog input for the A/D
• Clock input for TMR0
• External edge triggered interrupt
• Digital output from Comparator 1
FIGURE 4-3: BLOCK DIAGRAM OF RA2
4.2.3.4 RA3/MCLR
/VPP
Figure 4-4 shows the diagram for this pin. The RA3 pin
is configurable to function as one of the following:
• General purpose input
• Master Clear Reset with weak pull-up
FIGURE 4-4: BLOCK DIAGRAM OF RA3
I/O pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
Weak
ANS2
Data Bus
WR
WPUA
RD
WPUA
RD
PORTA
WR
PORTA
WR
TRISA
RD
TRISA
WR
IOCA
RD
IOCA
To A/D Converter
0
1
To INT
To TMR0
ANS2
RAPU
Interrupt-on-
Change
C1OUT
C1OE
D
EN
Q
D
EN
Q
D
EN
Q
Q1
Q3
RD PORTA
Input
V
SS
D
Q
CK
Q
RD
PORTA
WR
IOCA
RD
IOCA
Reset
MCLRE
RD
TRISA
VSS
MCLRE
VDD
Weak
MCLRE
Interrupt-on-
Change
pin
D
EN
Q
D
EN
Q
D
EN
Q
Q1
Q3
RD PORTA
D
Q
CK
Q
Data Bus
WR
WPUA
RD
WPUA
RAPU