Datasheet

PIC16F785/HV785

4.2.2 INTERRUPT-ON-CHANGE

Each of the PORTA pins is individually configurable as

an interrupt-on-change pin. Control bits IOCAx enable

or disable the interrupt function for each pin. Refer to

Power-on Reset.

For enabled interrupt-on-change pins, the values are

compared with the old value latched on the last read of

PORTA. The ‘mismatch’ outputs of the last read are

OR’d together to set, the PORTA Change Interrupt flag

bit (RAIF) in the INTCON register (Register 2-3).

This interrupt can wake the device from Sleep. The

user, in the Interrupt Service Routine, clears the inter-

rupt by:

a) Any read or write of PORTA. This will end the

mismatch condition, then,

b) Clear the flag bit RAIF.

A mismatch condition will continue to set flag bit RAIF.

Reading PORTA will end the mismatch condition and

allow flag bit RAIF to be cleared. The latch holding the

last read value is neither affected by an MCLR

nor BOR

Reset. After these resets, the RAIF flag will continue to

be set if a mismatch is present.

Note: If a change on the I/O pin should occur

when the read operation is being executed

(start of the Q2 cycle), then the RAIF

interrupt flag may not get set.

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— —IOCA5

(2)

IOCA4

(2)

IOCA3 IOCA2 IOCA1 IOCA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 IOCA<5:0>: Interrupt-on-change PORTA Control bits

(2)

1 = Interrupt-on-change enabled

0 = Interrupt-on-change disabled

Note 1: Global interrupt enable (GIE) must be enabled for individual interrupts to be recognized.

2: IOCA<5:4> always reads ‘1’ in XT, HS and LP OSC modes.