Datasheet

© 2008 Microchip Technology Inc. DS41249E-page 35
PIC16F785/HV785
4.0 I/O PORTS
There are seventeen general purpose I/O pins and one
input only pin available. Depending on which peripher-
als are enabled, some or all of the pins may not be
available as general purpose I/O. In general, when a
peripheral is enabled, the associated pin may not be
used as a general purpose I/O pin.
4.1 PORTA and TRISA Registers
PORTA is a 6-bit wide, bidirectional port. The corre-
sponding data direction register is TRISA (Register 4-2).
Setting a TRISA bit (= 1) will make the corresponding
PORTA pin an input (i.e., put the corresponding output
driver in a High-Impedance mode). Clearing a TRISA bit
(= 0) will make the corresponding PORTA pin an output
(i.e., put the contents of the output latch on the selected
pin). The exception is RA3, which is input only and its
TRIS bit will always read as ‘1’. Example 4-1 shows how
to initialize PORTA.
Reading the PORTA register (Register 4-1) reads the
status of the pins, whereas writing to it will write to the
port latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read; this value is modified and then
written to the port data latch. RA3 reads ‘0’ when
MCLRE = 1.
The TRISA register controls the direction of the
PORTA pins, even when they are being used as analog
inputs. The user must ensure the bits in the TRISA
register are maintained set when using them as analog
inputs. I/O pins configured as analog inputs always
read ‘0’.
When RA1 is configured as a voltage reference output,
the RA1 digital output driver will automatically be
disabled while not affecting the TRISA<1> value.
EXAMPLE 4-1: INITIALIZING PORTA
REGISTER 4-1: PORTA: PORTA REGISTER
Note: The ANSEL0 (91h) register must be initial-
ized to configure an analog channel as a
digital input. Pins configured as analog
inputs will read ‘0’.
BCF STATUS,RP0 ;Bank 0
BCF STATUS,RP1 ;
CLRF PORTA ;Init PORTA
MOVLW F8h ;Set RA<2:0> to
ANDWF ANSEL0,f ; digital I/O
BSF STATUS,RP0 ;Bank 1
MOVLW 0Ch ;Set RA<3:2> as inputs
MOVWF TRISA ; and set RA<5:4,1:0>
; as outputs
BCF STATUS,RP0 ;Bank 0
U-0 U-0 R/W-x R/W-x
(1)
R/W-x R/W-x
(1)
R/W-x
(1)
R/W-x
(1)
— —
RA5 RA4 RA3 RA2 RA1 RA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 RA<5:0>: PORTA I/O Pin bits
1 = Port pin is greater than V
IH
0 = Port pin is less than VIL
Note 1: Data latches are unknown after a POR, but each port bit reads ‘0’ when the corresponding
analog select bit is ‘1’ (see Register 12-1).