Datasheet

© 2008 Microchip Technology Inc. DS41249E-page 31
PIC16F785/HV785
FIGURE 3-7: TWO-SPEED START-UP
3.7 Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) is designed to
allow the device to continue to operate in the event of
an oscillator failure. The FSCM can detect oscillator
failure at any point after the device has exited a Reset
or Sleep condition and the Oscillator Start-up Timer
(OST) has expired.
FIGURE 3-8: FSCM BLOCK DIAGRAM
The FSCM function is enabled by setting the FCMEN
bit in Configuration Word (CONFIG). It is applicable to
all external clock options (LP, XT, HS, EC, RC or I/O
modes).
In the event of an external clock failure, the FSCM will
set the OSFIF bit in the PIR1 Register and generate an
oscillator fail interrupt if the OSFIE bit in the PIE1 Reg-
ister is set. The device will then switch the system clock
to the internal oscillator. The system clock will continue
to come from the internal oscillator unless the external
clock recovers and the Fail-Safe condition is exited.
The frequency of the internal oscillator will depend
upon the value contained in the IRCF bits
(OSCCON<6:4>). Upon entering the Fail-Safe condi-
tion, the OSTS bit in the OSCCON Register is automat-
ically cleared to reflect that the internal oscillator is
active and the WDT is cleared. The SCS bit in the OSC-
CON Register is not updated. Enabling FSCM does not
affect the LTS bit.
The FSCM sample clock is generated by dividing the
LFINTOSC clock by 64. This will allow enough time
between FSCM sample clocks for a system clock edge
to occur. Figure 3-8 shows the FSCM block diagram.
On the rising edge of the sample clock, the monitoring
latch (CM = 0) will be cleared. On a falling edge of the
primary system clock, the monitoring latch will be set
(CM = 1). In the event that a falling edge of the sample
clock occurs, and the monitoring latch is not set, a clock
failure has been detected. The assigned internal
oscillator is enabled when FSCM is enabled as
reflected by the IRCF bits.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
0 1 1022 1023
PC PC + 1 PC + 2
TOSTT
INTOSC
OSC1
OSC2
Program Counter
System Clock
Primary
LFINTOSC
÷ 64
S
C
Q
31 kHz
(~32 μs)
488 Hz
(~2 ms)
Clock Monitor
Latch (CM)
(edge-triggered)
Clock
Failure
Detected
Oscillator
Clock
Q
Note: Two-Speed Start-up is automatically
enabled when the Fail-Safe Clock Monitor
mode is enabled.