Datasheet
© 2008 Microchip Technology Inc. DS41249E-page 13
PIC16F785/HV785
TABLE 2-4: PIC16F785/HV785 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Page
Bank 2
100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 22,114
101h TMR0 Timer0 Module’s Register xxxx xxxx 49,114
102h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 21,114
103h STATUS IRP RP1 RP0 TO
PD ZDCC0001 1xxx 15,114
104h FSR Indirect Data Memory Address Pointer xxxx xxxx 22,114
105h PORTA
(1)
— — RA5 RA4 RA3 RA2 RA1 RA0 --x0 x000 35,114
106h PORTB
(1)
RB7 RB6 RB5 RB4 — — — — xx00 ---- 42,114
107h PORTC
(1)
RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 00xx 0000 45,114
108h — Unimplemented — —
109h — Unimplemented — —
10Ah PCLATH
— — — Write Buffer for Upper 5 bits of Program Counter ---0 0000 21,114
10Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 17,114
10Ch — Unimplemented — —
10Dh — Unimplemented — —
10Eh — Unimplemented — —
10Fh — Unimplemented — —
110h
PWMCON1 — COMOD1 COMOD0 CMDLY4 CMDLY3 CMDLY2 CMDLY1 CMDLY0 -000 0000 101,114
111h
PWMCON0 PRSEN PASEN BLANK2 BLANK1 SYNC1 SYNC0 PH2EN PH1EN 0000 0000 93,114
112h
PWMCLK PWMASE PWMP1 PWMP0 PER4 PER3 PER2 PER1 PER0 0000 0000 94,114
113h PWMPH1 POL C2EN C1EN PH4 PH3 PH2 PH1 PH0 0000 0000 95,114
114h PWMPH2 POL C2EN C1EN PH4 PH3 PH2 PH1 PH0 0000 0000 96,114
115h — Unimplemented — —
116h — Unimplemented — —
117h — Unimplemented — —
118h — Unimplemented — —
119h CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0 0000 0000 65,114
11Ah CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0 0000 0000 67,114
11Bh CM2CON1 MC1OUT MC2OUT
— — — — T1GSS C2SYNC 00-- --10 68,114
11Ch OPA1CON OPAON
— — — — — — — 0--- ---- 76,114
11Dh OPA2CON OPAON
— — — — — — — 0--- ---- 76,114
11Eh — Unimplemented — —
11Fh — Unimplemented — —
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: Port pins with analog functions controlled by the ANSEL0 and ANSEL1 registers will read ‘0’ immediately after a Reset even though the
data latches are either undefined (POR) or unchanged (other Resets).