Datasheet
PIC16F785/HV785
DS41249E-page 12 © 2008 Microchip Technology Inc.
TABLE 2-3: PIC16F785/HV785 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Page
Bank 1
80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 22,114
81h OPTION_REG RAPU
INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 17,114
82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 21,114
83h STATUS IRP RP1 RP0 TO
PD ZDCC0001 1xxx 15,114
84h FSR Indirect Data Memory Address Pointer xxxx xxxx 22,114
85h TRISA
— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 35,114
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4
— — — — 1111 ---- 42,114
87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 45,114
88h — Unimplemented — —
89h — Unimplemented — —
8Ah PCLATH
— — — Write Buffer for Upper 5 bits of Program Counter ---0 0000 21,114
8Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 000x 17,114
8Ch PIE1 EEIE ADIE CCP1IE C2IE C1IE OSFIE TMR2IE TMR1IE 0000 0000 18,114
8Dh — Unimplemented — —
8Eh PCON
— — — SBOREN — —PORBOR ---1 --qq 20,114
8Fh OSCCON
— IRCF2 IRCF1 IRCF0 OSTS
(1)
HTS LTS SCS -110 q000 33,114
90h OSCTUNE
— — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 28,114
91h ANSEL0 ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 82,114
92h PR2 Timer2 Module Period Register 1111 1111 55,114
93h ANSEL1
— — — — ANS11 ANS10 ANS9 ANS8 ---- 1111 82,114
94h — Unimplemented — —
95h WPUA
— — WPUA5 WPUA4 WPUA3
(2)
WPUA2 WPUA1 WPUA0 --11 1111 36,114
96h IOCA
— — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 37,114
97h — Unimplemented — —
98h REFCON
— — BGST VRBB VREN VROE CVROE — --00 000- 73,114
99h VRCON C1VREN C2VREN VRR
— VR3 VR2 VR1 VR0 000- 0000 72,114
9Ah EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 103,114
9Bh EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 103,114
9Ch EECON1
— — — — WRERR WREN WR RD ---- x000 104,114
9Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- 104,114
9Eh ADRESL Least Significant 2 bits of the left justified A/D result or 8 bits of the right justified result xxxx xxxx 81,114
9Fh ADCON1
— ADCS2 ADCS1 ADCS0 — — — — -000 ---- 84,114
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe mode is enabled, otherwise this
bit resets to ‘1’.
2: RA3 pull-up is enabled when MCLRE is ‘1’ in Configuration Word.