Datasheet

PIC16F785/HV785
DS41249E-page 124 © 2008 Microchip Technology Inc.
FIGURE 15-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT
(1)
15.7 Code Protection
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out using ICSP
™
for verification purposes.
15.8 ID Locations
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution, but are
readable and writable during Program/Verify. Only the
Least Significant 7 bits of the ID locations are used.
15.9 In-Circuit Serial Programming™
(ICSP™)
The PIC16F785/HV785 microcontrollers can be seri-
ally programmed while in the end application circuit.
This is simply done with five lines:
•Clock
•Data
•Power
•Ground
• Programming voltage
This allows customers to manufacture boards with
unprogrammed devices and then program the micro-
controller just before shipping the product. This also
allows the most recent firmware, or a custom firmware,
to be programmed.
The device is placed into a Program/Verify mode by
holding the RA0 and RA1 pins low, while raising the
MCLR
(VPP) pin from VIL to VIHH. See the “PIC16F785/
HV785 Memory Programming Specification”
(DS41237) for more information. RA0 becomes the
programming data and RA1 becomes the programming
clock. Both RA0 and RA1 are Schmitt Trigger inputs in
this mode.
After Reset, to place the device into Program/Verify
mode, the Program Counter (PC) is at location 00h. A
6-bit command is then supplied to the device.
Depending on the command, 14 bits of program data
are then supplied to or from the device, depending on
whether the command was a load or a read. For
complete details of serial programming, please refer to
the “PIC16F785/HV785 Memory Programming Speci-
fication” (DS41237).
A typical In-Circuit Serial Programming connection is
shown in Figure 15-11.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT
(4)
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
PC PC + 1 PC + 2
Inst(PC) = Sleep
Inst(PC - 1)
Inst(PC + 1)
Sleep
Processor
in Sleep
Interrupt Latency
(3)
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h)
Inst(0005h)
Inst(0004h)
Dummy cycle
PC + 2 0004h 0005h
Dummy cycle
T
OST
(2)
PC + 2
Note 1: XT, HS or LP Oscillator mode assumed.
2: T
OST = 1024TOSC (drawing not to scale). This delay does not apply to EC, RC and INTOSC Oscillator modes or Two-Speed Start-up
(see Section 3.6 “Two-Speed Clock Start-up Mode”).
3: GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h.
If GIE = 0, execution will continue in-line.
4: CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.
Note: If the code protection is turned off, the
entire data EEPROM and Flash program
memory will be erased by performing a
bulk erase command. See the
“PIC16F785/HV785 Memory Program-
ming Specification” (DS41237) for more
information.