Datasheet

© 2008 Microchip Technology Inc. DS41249E-page 119
PIC16F785/HV785
FIGURE 15-8: INT PIN INTERRUPT TIMING
TABLE 15-6: SUMMARY OF INTERRUPT REGISTERS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on all
other Resets
INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000
PIE1 EEIE ADIE CCP1IE C2IE C1IE OSFIE TMR2IE TMR1IE 0000 0000 0000 0000
PIR1
EEIF ADIF CCP1IF C2IF C1IF OSFIF TMR2IF TMR1IF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’, q = value depends upon condition. Shaded cells are not
used by the Interrupt module.
Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4
OSC1
CLKOUT
INT pin
INTF Flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
Interrupt Latency
PC
PC + 1
PC + 1
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (PC)
Inst (PC + 1)
Inst (PC - 1)
Inst (0004h)
Dummy Cycle
Inst (PC)
—
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-4 T
CY. Synchronous latency = 3 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in INTOSC and RC Oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 19.0 “Electrical Specifications”.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
(1)
(2)
(3)
(4)
(5)
(1)