Datasheet

PIC16F785/HV785
DS41249E-page 118 © 2008 Microchip Technology Inc.
15.3.1 RA2/AN2/T0CKI/INT/C1OUT
INTERRUPT
External interrupt on RA2/AN2/T0CKI/INT/C1OUT pin
is edge-triggered; either rising, if INTEDG bit of the
OPTION Register is set, or falling, if INTEDG bit is
clear. When a valid edge appears on the RA2/AN2/
T0CKI/INT/C1OUT pin, the INTF bit of the INTCON
Register is set. This interrupt can be disabled by clear-
ing the INTE control bit of the INTCON Register. The
INTF bit must be cleared in software in the Interrupt
Service Routine before re-enabling this interrupt. The
RA2/AN2/T0CKI/INT/C1OUT interrupt can wake-up
the processor from Sleep if the INTE bit was set prior to
going into Sleep. The status of the GIE bit decides
whether or not the processor branches to the interrupt
vector following wake-up (0004h). See Section 15.6
“Power-Down Mode (Sleep)” for details on Sleep and
Figure 15-10 for timing of wake-up from Sleep through
RA2/AN2/T0CKI/INT/C1OUT interrupt.
15.3.2 TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
the T0IF bit of the INTCON Register. The interrupt can
be enabled/disabled by setting/clearing T0IE bit of the
INTCON Register. See Section 5.0 “Timer0 Module”
for operation of the Timer0 module.
15.3.3 PORTA INTERRUPT
An input change on PORTA change sets the RAIF of
the INTCON Register bit. The interrupt can be enabled/
disabled by setting/clearing the RAIE bit of the INTCON
Register. Plus, individual pins can be configured
through the IOCA register.
FIGURE 15-7: INTERRUPT LOGIC
Note: The ANSEL0 (91h), and ANSEL1 (93h)
registers must be initialized to configure
an analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RAIF inter-
rupt flag may not get set.
TMR1IF
TMR1IE
C1IF
C1IE
T0IF
T0IE
INTF
INTE
RAIF
RAIE
GIE
PEIE
Wake-up (If in Sleep mode)
(1)
Interrupt to CPU
EEIE
EEIF
ADIF
ADIE
IOC-RA0
IOCA0
IOC-RA1
IOCA1
IOC-RA2
IOCA2
IOC-RA3
IOCA3
IOC-RA4
IOCA4
IOC-RA5
IOCA5
TMR2IF
TMR2IE
CCP1IF
CCP1IE
OSFIF
OSFIE
C2IF
C2IE
Note 1: Some peripherals depend upon the system clock for
operation. Since the system clock is suspended during Sleep, only
those peripherals which do not depend upon the system clock will wake
the part from Sleep. See Section 15.6.1 “Wake-up from Sleep”.