Datasheet

© 2008 Microchip Technology Inc. DS41249E-page 117
PIC16F785/HV785
15.3 Interrupts
The PIC16F785/HV785 has 11 sources of interrupt:
• External Interrupt RA2/INT
• TMR0 Overflow Interrupt
• PORTA Change Interrupt
• 2 Comparator Interrupts
• A/D Interrupt
• Timer1 Overflow Interrupt
• Timer2 Match Interrupt
• EEPROM Data Write Interrupt
• Fail-Safe Clock Monitor Interrupt
• CCP Interrupt
The Interrupt Control register (INTCON) and Peripheral
Interrupt register (PIR1) record individual interrupt
requests in flag bits. The INTCON register also has
individual and global interrupt enable bits.
A Global Interrupt Enable bit, GIE of the INTCON Reg-
ister enables (if set) all unmasked interrupts, or dis-
ables (if cleared) all interrupts. Individual interrupts can
be disabled through their corresponding enable bits in
INTCON register and PIE1 register. GIE is cleared on
Reset.
The Return from Interrupt instruction,
RETFIE, exits
interrupt routine, as well as sets the GIE bit, which
re-enables unmasked interrupts.
The following interrupt flags are contained in the INT-
CON register:
• INT Pin Interrupt
• PORTA Change Interrupt
• TMR0 Overflow Interrupt
The peripheral interrupt flags are contained in the
special register PIR1. The corresponding interrupt
enable bit is contained in special register PIE1.
The following interrupt flags are contained in the PIR1
register:
• EEPROM Data Write Interrupt
• A/D Interrupt
• 2 Comparator Interrupts
• Timer1 Overflow Interrupt
• Timer2 Match Interrupt
• Fail-Safe Clock Monitor Interrupt
• CCP Interrupt
When an interrupt is serviced:
• The GIE is cleared to disable any further interrupt
• The return address is PUSHed onto the stack
• The PC is loaded with 0004h
For external interrupt events, such as the INT pin or
PORTA change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends upon when the interrupt event occurs (see
Figure 15-8). The latency is the same for one or two-
cycle instructions. Once in the Interrupt Service
Routine, the source(s) of the interrupt can be
determined by polling the interrupt flag bits. The
interrupt flag bit(s) must be cleared in software before
re-enabling interrupts to avoid multiple interrupt
requests.
For additional information on Timer1, Timer2,
comparators, A/D, Data EEPROM or CCP modules,
refer to the respective peripheral section.
Note 1: Individual interrupt flag bits are set,
regardless of the status of their
corresponding mask bit or the GIE bit.
2: When an instruction that clears the GIE
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The interrupts, which were
ignored, are still pending to be serviced
when the GIE bit is set again.