Datasheet

PIC16F785/HV785
DS41249E-page 112 © 2008 Microchip Technology Inc.
15.2.6 TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows: first,
PWRT time out is invoked after POR has expired, then
OST is activated after the PWRT time out has expired.
The total time out will vary based on oscillator configu-
ration and PWRTE
bit status. For example, in EC mode
with PWRTE
bit equal to ‘1’ (PWRT disabled), there will
be no time out at all. Figure 15-4, Figure 15-6 and
Figure 15-6 depict time-out sequences. The device can
execute code from the INTOSC, while OST is active by
enabling Two-Speed Start-up or Fail-Safe Monitor (see
Section 3.6.2 “Two-Speed Start-up Sequence” and
Section 3.7 “Fail-Safe Clock Monitor”).
Since the time outs occur from the POR pulse, if MCLR
is kept low long enough, the time outs will expire. Then
bringing MCLR
high will begin execution immediately
(see Figure 15-6). This is useful for testing purposes or
to synchronize more than one PIC16F785/HV785
device operating in parallel.
Table 15-5 shows the Reset conditions for some
special registers, while Table 15-4 shows the Reset
conditions for all the registers.
15.2.7 POWER CONTROL (PCON)
REGISTER
The Power Control register (address 8Eh) has two Sta-
tus bits to indicate what type of Reset that last
occurred.
Bit 0 is BOR
(Brown-out Reset). BOR is unknown on
Power-on Reset. It must then be set by the user and
checked on subsequent Resets to see if BOR = 0,
indicating that a Brown-out has occurred. The BOR
Status bit is a “don’t care” and is not necessarily
predictable if the brown-out circuit is disabled
(BOREN<1:0> = 00 in the Configuration Word).
Bit 1 is POR
(Power-on Reset). It is ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a
subsequent Reset, if POR
is ‘0’, it will indicate that a
Power-on Reset has occurred (i.e., V
DD may have
gone too low).
For more information, see Section 15.2.4 “Brown-Out
Reset (BOR)”.
TABLE 15-1: TIME OUT IN VARIOUS SITUATIONS
TABLE 15-2: STATUS/PCON BITS AND THEIR SIGNIFICANCE
TABLE 15-3: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT
Oscillator Configuration
Power-up Brown-out Reset
Wake-up from
Sleep
PWRTE = 0 PWRTE = 1 PWRTE = 0 PWRTE = 1
XT, HS, LP T
PWRT +
1024•T
OSC
1024•TOSC TPWRT +
1024•T
OSC
1024•TOSC 1024•TOSC
RC, EC, INTOSC TPWRT —TPWRT ——
POR BOR TO PD Condition
0x11Power-on Reset
u011Brown-out Reset
uu0uWDT Reset
uu00WDT Wake-up
uuuuMCLR
Reset during normal operation
uu10MCLR
Reset during Sleep
Legend: u = unchanged, x = unknown
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on all
other Resets
PCON
— — —SBOREN — —PORBOR ---1 --qq ---1 --qq
STATUS
IRP RP1 RP0 TO PD Z DC C 0001 1xxx 0001 1xxx
Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are
not used by BOR.
Note 1: Other (non Power-up) Resets include MCLR
Reset and Watchdog Timer Reset during normal operation.