Datasheet

PIC16F785/HV785
DS41249E-page 110 © 2008 Microchip Technology Inc.
15.2.1 POWER-ON RESET
The on-chip POR circuit holds the chip in Reset until
V
DD has reached a high enough level for proper
operation. A minimum rise rate for V
DD is required. See
Section 19.0 “Electrical Specifications” for details. If
the BOR is enabled, the minimum rise rate specifica-
tion does not apply. The BOR circuitry will keep the
device in Reset until VDD reaches VBOR (see
Section 15.2.4 “Brown-Out Reset (BOR)”)
The POR circuit, on this device, has a POR re-arm cir-
cuit. This circuit is designed to ensure a re-arm of the
POR circuit if V
DD drops below a preset re-arming volt-
age (V
PARM) for at least the minimum required time.
Once V
DD is below the re-arming point for the minimum
required time, the POR Reset will reactivate and
remain in Reset until VDD returns to a value greater
than V
POR. At this point, a 1 μs (typical) delay will be ini-
tiated to allow V
DD to continue to ramp to a voltage
safely above V
POR.
When the device starts normal operation (exits the
Reset condition), device operating parameters
(i.e., voltage, frequency, temperature, etc.) must be
met to ensure operation. If these conditions are not
met, the device must be held in Reset until the
operating conditions are met.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
15.2.2 MASTER CLEAR (MCLR)
PIC16F785/HV785 has a noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
It should be noted that a WDT Reset does not drive
MCLR
pin low.
The behavior of the ESD protection on the MCLR
pin
has been altered from earlier devices of this family.
Voltages applied to the pin that exceed its specification
can result in both MCLR
Resets and excessive current
beyond the device specification during the ESD event.
For this reason, Microchip recommends that the MCLR
pin no longer be tied directly to VDD. The use of an RC
network, as shown in Figure 15-1, is suggested.
FIGURE 15-2: RECOMMENDED MCLR
CIRCUIT
An internal MCLR option is enabled by clearing the
MCLRE bit in the Configuration Word. When cleared,
MCLR is internally tied to VDD and an internal Weak
Pull-up is enabled for the MCLR
pin. The VPP function
of the RA3/MCLR
/VPP pin is not affected by selecting
the internal MCLR
option.
15.2.3 POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 64 ms (nominal)
time out on power-up only, from POR or Brown-out
Reset. The Power-up Timer operates from the 31 kHz
LFINTOSC oscillator. For more information, see
Section 3.4 “Internal Clock Modes”. The chip is kept
in Reset as long as PWRT is active. The PWRT delay
allows the V
DD to rise to an acceptable level. A config-
uration bit, PWRTE
can disable (if ‘1’) or enable (if ‘0’)
the Power-up Timer. The Power-up Timer should be
enabled when Brown-out Reset is enabled, although it
is not required.
The Power-up Time Delay will vary from chip-to-chip
and vary due to:
•V
DD variation
• Temperature variation
• Process variation
See DC parameters for details (Section 19.0
“Electrical Specifications”).
15.2.4 BROWN-OUT RESET (BOR)
The BOREN0 and BOREN1 bits in the Configuration
Word select one of four BOR modes. Two modes have
been added to allow software or hardware control of
the BOR enable. When BOREN<1:0> = 01, the SBO-
REN bit of the PCON Register enables/disables the
BOR allowing it to be controlled in software. By select-
ing BOREN<1:0>, the BOR is automatically disabled in
Sleep to conserve power, and enabled on wake-up. In
this mode, the SBOREN bit is disabled. See
Register 15.2 for the Configuration Word definition.
If V
DD falls below VBOR for greater than parameter
(T
BOR), see Section 19.0 “Electrical Specifica-
tions”, the Brown-out situation will reset the device.
This will occur regardless of the V
DD slew rate. A Reset
is not assured if V
DD falls below VBOR for less than
parameter (T
BOR).
On any Reset (Power-on, Brown-out Reset, Watchdog,
etc.), the chip will remain in Reset until V
DD rises above
V
BOR (see Figure 15-3). The Power-up Timer will now
be invoked, if enabled, and will keep the chip in Reset
an additional 64 ms.
If V
DD drops below VBOR while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power-up Timer will be re-initialized. Once V
DD
rises above VBOR, the Power-up Timer will execute a
64 ms Reset.
VDD
RA3/MCLR/VPP
R1
1kΩ (or greater)
C1
0.1 μF
(optional, not critical)
PIC16F785/HV785
Note: The Power-up Timer is enabled by the
PWRTE
bit in the Configuration Word.