Datasheet

© 2008 Microchip Technology Inc. DS41249E-page 101
PIC16F785/HV785
REGISTER 13-5: PWMCON1: PWM CONTROL REGISTER 1
FIGURE 13-5: COMPLEMENTARY OUTPUT PWM BLOCK DIAGRAM
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— COMOD1 COMOD0 CMDLY4 CMDLY3 CMDLY2 CMDLY1 CMDLY0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6-5
COMOD<1:0>: Complementary Mode Select bits
(1)
00 = Normal two-phase operation. Complementary mode is disabled.
01 = Complementary operation. Duty cycle is terminated by C1OUT or C2OUT.
10 = Complementary operation. Duty cycle is terminated by PWMPH2<4:0> = pwm_count.
11 = Complementary operation. Duty cycle is terminated by PWMPH2<4:0> = pwm_count or C1OUT or C2OUT.
bit 4-0
CMDLY<4:0>: Complementary Drive Dead Time bits (typical)
00000 =Delay = 0
00001 = Delay = 5 ns
00010 = Delay = 10 ns
••••• =• • •
11111 = Delay = 155 ns
Note 1: PWMCON0<1:0> must be set to ‘11’ for Complementary mode operation.
Prescale
PWMPH1<C1EN>
PWMPH1<C2EN>
PWMPH2<4:0>
PWMPH2<POL>
PWMPH1<POL>
PWMPH1<4:0>
FOSC
C1OUT
C2OUT
PS<1:0>
pwm_clk
pha1
pha2
pwm_reset
Delay
S
R
(1)
Q
01
10
delay
S
R
(1)
Q
COMOD<1:0>
CMDLY<4:0>
5
5
11
RC1/AN5/C12IN1-/PH1
RC4/C2OUT/PH2
Phase
Counter
PER<4:0>
5
pwm_count
0
1
PWMASE
MASTER
M
S
Res
PH1EN
PH2EN
PASEN
5
RB7/SYNC
5
5
pwm_reset
Shutdown
Shutdown
Note 1: Reset dominant.