PIC16F785/HV785 Data Sheet 20-Pin Flash-Based, 8-Bit CMOS Microcontroller with Two-Phase Asynchronous Feedback PWM Dual High-Speed Comparators and Dual Operational Amplifiers © 2008 Microchip Technology Inc.
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PIC16F785/HV785 20-Pin Flash-Based 8-Bit CMOS Microcontroller High-Performance RISC CPU: Peripheral Features: • Only 35 Instructions to Learn: - All single-cycle instructions except branches • Operating Speed: - DC – 20 MHz oscillator/clock input - DC – 200 ns instruction cycle • Interrupt Capability • 8-Level Seep Hardware Stack • Direct, Indirect and Relative Addressing modes • High-Speed Comparator module with: - Two independent analog comparators - Programmable on-chip voltage reference (CVREF) modul
PIC16F785/HV785 Program Memory Data Memory Device Two10-bit Op Timers Shunt Comparators CCP Phase A/D (ch) Amps 8/16-bit Reg.
PIC16F785/HV785 RA3/MCLR/VPP RC5/CCP1 RC4/C2OUT/PH2 RC3/AN7/C12IN3-/OP1 RC6/AN8/OP1- 1 2 3 4 5 RA1/AN1/C12IN0-/VREF/ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RC0/AN4/C2IN+ RC1/AN5/C12IN1-/PH1 RC2/AN6/C12IN2-/OP2 15 14 13 12 11 6 7 8 9 10 20-PIN QFN 20 19 18 17 16 RA4/AN3/T1G/OSC2/CLKOUT RA5/T1CKI/OSC1/CLKIN VDD VSS RA0/AN0/C1IN+/ICSPDAT QFN (4x4x0.
PIC16F785/HV785 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 5 2.0 Memory Organization ................................................................................................................................................................... 9 3.0 Clock Sources .............................................................................
PIC16F785/HV785 1.0 DEVICE OVERVIEW This document contains device specific information for the PIC16F785/HV785. It is available in 20-pin PDIP, SOIC, SSOP and QFN packages. Figure 1-1 shows a block diagram of the PIC16F785/HV785 device. Table 1-1 shows the pinout description.
PIC16F785/HV785 TABLE 1-1: PIC16F785/HV785 PINOUT DESCRIPTION Name RA0/AN0/C1IN+/ICSPDAT RA1/AN1/C12IN0-/VREF/ ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RA3/MCLR/Vpp RA4/AN3/T1G/OSC2/ CLKOUT RA5/T1CKI/OSC1/CLKIN RB4/AN10/OP2- RB5/AN11/OP2+ RB6 RB7/SYNC RC0/AN4/C2IN+ Function Input Type RA0 TTL AN0 AN Output Type Description CMOS PORTA I/O with prog.
PIC16F785/HV785 TABLE 1-1: PIC16F785/HV785 PINOUT DESCRIPTION (CONTINUED) Name RC1/AN5/C12IN1-/PH1 RC2/AN6/C12IN2-/OP2 RC3/AN7/C12IN3-/OP1 RC4/C2OUT/PH2 RC5/CCP1 RC6/AN8/OP1- RC7/AN9/OP1+ Function Input Type RC1 TTL AN5 AN C12IN1- AN PH1 — RC2 TTL AN6 AN C12IN2OP2 RC3 TTL AN7 AN C12IN3OP1 RC4 TTL C2OUT — Output Type Description CMOS PORTC I/O — A/D Channel 5 input — Comparator 1 and 2 inverting input CMOS PWM phase 1 output CMOS PORTC I/O — A/D Channel 6 input AN — Co
PIC16F785/HV785 NOTES: DS41249E-page 8 © 2008 Microchip Technology Inc.
PIC16F785/HV785 2.0 MEMORY ORGANIZATION 2.1 Program Memory Organization The PIC16F785/HV785 has a 13-bit program counter capable of addressing an 8k x 14 program memory space. Only the first 2k x 14 (0000h-07FFh) for the PIC16F785/HV785 is physically implemented. Accessing a location above these boundaries will cause a wrap around within the first 2k x 14 space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1).
PIC16F785/HV785 FIGURE 2-2: DATA MEMORY MAP OF THE PIC16F785/HV785 File Address Indirect addr.(1) TMR0 PCL STATUS FSR PORTA PORTB PORTC PCLATH INTCON PIR1 TMR1L TMR1H T1CON TMR2 T2CON CCPR1L CCPR1H CCP1CON WDTCON ADRESH ADCON0 File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch Indirect addr.
PIC16F785/HV785 TABLE 2-2: Addr Name PIC16F785/HV785 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 22,114 01h TMR0 Timer0 Module’s Register xxxx xxxx 49,114 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 21,114 03h STATUS 15,114 04h FSR 05h PORTA(1) IRP RP1 RP0 TO PD
PIC16F785/HV785 TABLE 2-3: Addr PIC16F785/HV785 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page xxxx xxxx 22,114 1111 1111 17,114 Bank 1 80h INDF 81h OPTION_REG Addressing this location uses contents of FSR to address data memory (not a physical register) 82h PCL 83h STATUS 84h FSR 85h TRISA RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Program Counter’s (PC) Least Significant Byte IRP RP1 RP0 — TRISA5 2
PIC16F785/HV785 TABLE 2-4: Addr Name PIC16F785/HV785 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page Bank 2 100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 22,114 101h TMR0 Timer0 Module’s Register xxxx xxxx 49,114 102h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 21,114 103h STATUS 15,114 104h FSR 105h PORTA(1) IRP RP1 RP0 TO
PIC16F785/HV785 TABLE 2-5: Addr Name PIC16F785/HV785 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page xxxx xxxx 22,114 1111 1111 17,114 Bank 3 180h INDF 181h OPTION_RE G Addressing this location uses contents of FSR to address data memory (not a physical register) 182h PCL 183h STATUS RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Program Counter’s (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C Indirect Dat
PIC16F785/HV785 2.2.2.1 STATUS Register The STATUS register contains arithmetic status of the ALU, the Reset status and the bank select bits for data memory (SRAM). The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable.
PIC16F785/HV785 2.2.2.2 OPTION_REG Register Note: The Option register is a readable and writable register, which contains various control bits to configure the TMR0/WDT prescaler, the external RA2/INT interrupt, the TMR0 and the weak pull-ups on PORTA. REGISTER 2-2: To achieve a 1:1 prescaler assignment for TMR0, assign the prescaler to the WDT by setting PSA bit to ‘1’ in the OPTION Register. See Section 5.4 “Prescaler”.
PIC16F785/HV785 2.2.2.3 INTCON Register Note: The Interrupt Control register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, PORTA change and external RA2/INT pin interrupts. REGISTER 2-3: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE bit of the INTCON register.
PIC16F785/HV785 2.2.2.4 PIE1 Register Note: The Peripheral Interrupt Enable Register 1 contains the interrupt enable bits, as shown in Register 2-4. REGISTER 2-4: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
PIC16F785/HV785 2.2.2.5 PIR1 Register The Peripheral Interrupt Register 1 contains the interrupt flag bits. REGISTER 2-5: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE, in the INTCON Register). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16F785/HV785 2.2.2.6 PCON Register The Power Control register contains flag bits to allow differentiation between a Power-on Reset (POR), a Brown-out Reset (BOR), a Watchdog Timer (WDT) Reset (WDT) and an external MCLR Reset.
PIC16F785/HV785 2.3 PCL and PCLATH The Program Counter (PC) specifies the address of the instruction to fetch for execution. The program counter is 13 bits wide. The low byte is called the PCL register. The PCL register is readable and writable. The high byte of the PC Register is called the PCH register. This register contains PC<12:8> bits which are not directly readable or writable. All updates to the PCH register goes through the PCLATH register. On any Reset, the PC is cleared.
PIC16F785/HV785 2.4 Indirect Addressing, INDF and FSR Registers A simple program to clear RAM location 20h-2Fh using indirect addressing is shown in Example 2-1. The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. EXAMPLE 2-1: MOVLW MOVWF NEXT CLRF INCF BTFSS GOTO CONTINUE Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the File Select Register (FSR).
PIC16F785/HV785 3.0 CLOCK SOURCES The PIC16F785/HV785 can be configured in one of eight clock modes. 3.1 Overview 1. 2. The PIC16F785/HV785 has a wide variety of clock sources and selection features to allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 3-1 illustrates a block diagram of the PIC16F785/HV785 clock sources. 3. 4. 5.
PIC16F785/HV785 3.2 Clock Source Modes 3.3 Clock Source modes can be classified as external or internal. External Clock Modes 3.3.1 • External Clock modes rely on external circuitry for the clock source. Examples are oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT, and HS modes) and resistorcapacitor (RC mode) circuits. • Internal clock sources are contained internally within the PIC16F785/HV785.
PIC16F785/HV785 3.3.3 FIGURE 3-4: LP, XT, HS MODES The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to the OSC1 and OSC2 pins (Figure 3-1). The mode selects a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed.
PIC16F785/HV785 TABLE 3-3: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR In RCIO mode, the RC circuit is connected to the OSC1 pin. The OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 4 of PORTA (RA4). Figure 3-6 shows the RCIO mode connections. Crystal Freq. Cap. Range C1 Cap.
PIC16F785/HV785 3.4 Internal Clock Modes The PIC16F785/HV785 has two independent, internal oscillators that can be configured or selected as the system clock source. 1. 2. The HFINTOSC (High-frequency Internal Oscillator) is factory calibrated and operates at 8 MHz. The frequency of the HFINTOSC can be user adjusted ±12% via software using the OSCTUNE register (Register 3-1). The LFINTOSC (Low-frequency Internal Oscillator) is uncalibrated and operates at approximately 31 kHz.
PIC16F785/HV785 3.4.2.2 OSCTUNE Register The HFINTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 3-1). The OSCTUNE register has a nominal tuning range of ±12%. The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number. Due to process variation, the monotonicity and frequency step cannot be specified.
PIC16F785/HV785 3.4.3 LFINTOSC The Low-frequency Internal Oscillator (LFINTOSC) is an uncalibrated (approximate) 31 kHz internal clock source. The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). 31 kHz can be selected via software using the IRCF bits (see Section 3.4.4 “Frequency Select Bits (IRCF)”). The LFINTOSC is also the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM).
PIC16F785/HV785 3.5 Clock Switching The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bit. 3.5.1 SYSTEM CLOCK SELECT (SCS) BIT The System Clock Select (SCS) bit, in the OSCCON Register, selects the system clock source that is used for the CPU and peripherals. • When SCS = 0, the system clock source is determined by configuration of the FOSC<2:0> bits in Configuration Word (CONFIG).
PIC16F785/HV785 FIGURE 3-7: TWO-SPEED START-UP Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 INTOSC TOST OSC1 0 1 1022 1023 OSC2 PC Program Counter PC + 1 PC + 2 System Clock 3.7 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) is designed to allow the device to continue to operate in the event of an oscillator failure. The FSCM can detect oscillator failure at any point after the device has exited a Reset or Sleep condition and the Oscillator Start-up Timer (OST) has expired.
PIC16F785/HV785 3.7.1 FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared after a Reset, the execution of a SLEEP instruction, or a modification of the SCS bit. While in Fail-Safe condition, the PIC16F785/HV785 uses the internal oscillator as the system clock source. The IRCF bits in the OSCCON Register can be modified to adjust the internal oscillator frequency without exiting the Fail-Safe condition. The Fail-Safe condition must be cleared before the OSFIF flag can be cleared.
PIC16F785/HV785 REGISTER 3-2: OSCCON: OSCILLATOR CONTROL REGISTER U-0 R/W-1 R/W-1 R/W-0 R-q R-0 R-0 R/W-0 — IRCF2 IRCF1 IRCF0 OSTS(1) HTS LTS SCS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits 000 = 31 kHz 001 = 125 kHz 010 = 250 kHz 011 = 500 kHz 100 = 1 MHz 101 = 2 MHz
PIC16F785/HV785 TABLE 3-4: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets CONFIG CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — — OSCCON — IRCF2 IRCF1 IRCF0 OSTS HTS LTS SCS -110 q000 -110 q000 OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu PIE1 EEIE ADIE CCP1IE C2IE C1IE OSFIE TMR2IE TMR1IE 0000 0000 0000 0000 PIR1 EEIF ADIF CCP1IF C2IF
PIC16F785/HV785 4.0 I/O PORTS There are seventeen general purpose I/O pins and one input only pin available. Depending on which peripherals are enabled, some or all of the pins may not be available as general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin. 4.1 PORTA and TRISA Registers PORTA is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 4-2).
PIC16F785/HV785 REGISTER 4-2: U-0 — TRISA: PORTA TRI-STATE REGISTER U-0 R/W-1 R/W-1 R-1 R/W-1 R/W-1 R/W-1 — TRISA5(2) TRISA4(2) TRISA3(1) TRISA2 TRISA1 TRISA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TRISA<5:0>: PORTA Tri-State Control bit(1), (2) 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configu
PIC16F785/HV785 4.2.2 INTERRUPT-ON-CHANGE Each of the PORTA pins is individually configurable as an interrupt-on-change pin. Control bits IOCAx enable or disable the interrupt function for each pin. Refer to Register 4-4. The interrupt-on-change is disabled on a Power-on Reset. For enabled interrupt-on-change pins, the values are compared with the old value latched on the last read of PORTA.
PIC16F785/HV785 4.2.3 PORTA PIN DESCRIPTIONS AND DIAGRAMS Each PORTA pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the comparator or the A/D, refer to the appropriate section in this Data Sheet. 4.2.3.1 RA0/AN0/C1IN+/ICSPDAT Figure 4-1 shows the diagram for this pin.
PIC16F785/HV785 4.2.3.3 4.2.3.4 RA2/AN2/T0CKI/INT/C1OUT RA3/MCLR/VPP Figure 4-3 shows the diagram for this pin. The RA2 pin is configurable to function as one of the following: Figure 4-4 shows the diagram for this pin.
PIC16F785/HV785 4.2.3.5 RA4/AN3/T1G/OSC2/CLKOUT 4.2.3.6 RA5/T1CKI/OSC1/CLKIN Figure 4-5 shows the diagram for this pin. The RA4 pin is configurable to function as one of the following: Figure 4-6 shows the diagram for this pin.
PIC16F785/HV785 TABLE 4-1: Name ANSEL0 CM1CON0 CM2CON1 IOCA OPTION_REG REFCON Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111 C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0 0000 0000 0000 0000 — — — — T1GSS C2SYNC 00-- --10 00-- --10 MC1OUT MC2OUT INTCON PORTA SUMMARY OF REGISTERS ASSOCIATED WITH PORTA GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000
PIC16F785/HV785 4.3 PORTB and TRISB Registers The TRISB register controls the direction of the PORTB pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISB register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘0’. PORTB is a 4-bit wide, bidirectional port. The corresponding data direction register is TRISB (Register 46). Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e.
PIC16F785/HV785 4.3.1 PORTB PIN DESCRIPTIONS AND DIAGRAMS Each PORTB pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the PWM, operational amplifier, or the A/D, refer to the appropriate section in this Data Sheet. 4.3.1.1 FIGURE 4-8: WR TRISB CK CK Q VSS RD TRISB Q D 4.3.1.
PIC16F785/HV785 TABLE 4-2: Name ANSEL1 OPA2CON PORTB SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets — — — — ANS11 ANS10 ANS9 ANS8 ---- 1111 ---- 1111 OPAON — — — — — — — 0--- ---- 0--- ---- RB7 RB6 RB5 RB4 — — — — xxxx ---- uuuu ---- PWMCON0 PRSEN PASEN BLANK2 BLANK1 SYNC1 SYNC0 PH2EN PH1EN 0000 0000 0000 0000 TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 1111 ----
PIC16F785/HV785 4.4 PORTC and TRISC Registers PORTC is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISC (Register 48). Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). Example 4-3 shows how to initialize PORTC.
PIC16F785/HV785 4.4.1 PORTC PIN DESCRIPTIONS AND DIAGRAMS Each PORTC pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the comparator or the A/D, refer to the appropriate section in this Data Sheet. 4.4.1.1 4.4.1.
PIC16F785/HV785 4.4.1.5 4.4.1.7 RC2/AN6/C12IN2-/OP2 RC4/C2OUT/PH2 The RC2 is configurable to function as one of the following: The RC4 is configurable to function as one of the following: • • • • • General purpose I/O • Digital output from Comparator 2 • Digital output from the Two-Phase PWM General purpose I/O Analog input for the A/D Converter Analog input to Comparators 1 and 2 Analog output from Op Amp 2 FIGURE 4-13: 4.4.1.
PIC16F785/HV785 4.4.1.
PIC16F785/HV785 5.0 TIMER0 MODULE RA2/AN2/T0CKI/INT/C1OUT. The incrementing edge is determined by the source edge (T0SE) control bit of the OPTION Register. Clearing the T0SE bit selects the rising edge.
PIC16F785/HV785 5.3 5.4.1 Using Timer0 with an External Clock The prescaler assignment is fully under software control (i.e., it can be changed “on the fly” during program execution). To avoid an unintended device Reset, the following instruction sequence (Example 51 and Example 5-2) must be executed when changing the prescaler assignment between Timer0 and WDT. When no prescaler is used, the external clock input is the same as the prescaler output.
PIC16F785/HV785 6.0 TIMER1 MODULE WITH GATE CONTROL The Timer1 Control register (T1CON), shown in Register 6-1, is used to enable/disable Timer1 and select the various features of the Timer1 module. The Timer1 module is the 16-bit counter of the PIC16F785/HV785. Figure 6-1 shows the basic block diagram of the Timer1 module.
PIC16F785/HV785 6.1 Timer1 Modes of Operation Timer1 can operate in one of three modes: • 16-bit Timer with prescaler • 16-bit Synchronous counter • 16-bit Asynchronous counter In Timer mode, Timer1 is incremented on every instruction cycle. In Counter mode, Timer1 is incremented on the rising edge of the external clock input T1CKI. In addition, the Counter mode clock can be synchronized to the microcontroller system clock or run asynchronously.
PIC16F785/HV785 REGISTER 6-1: R/W-0 (1) T1GINV T1CON: TIMER1 CONTROL REGISTER R/W-0 TMR1GE (2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 T1GINV: Timer1 Gate Invert bit (1) 1 = Timer1 gate is high true (see bit 6) 0 = Timer1 gate is low true (see bit 6) bit 6 TMR1GE: Timer1 Gate Enable bit (2)
PIC16F785/HV785 6.5 Timer1 Operation in Asynchronous Counter Mode 6.6 A crystal oscillator circuit is built-in between pins OSC1 (input) and OSC2 (amplifier output). It is enabled by setting control bit T1OSCEN of the T1CON Register. The oscillator is a low power oscillator rated for 32.768 kHz. It will continue to run during Sleep. It is primarily intended for a 32.768 kHz tuning fork crystal. If control bit T1SYNC of the T1CON Register is set, the external clock input is not synchronized.
PIC16F785/HV785 7.0 TIMER2 MODULE 7.1 The Timer2 module timer is an 8-bit timer with the following features: • • • • • 8-bit timer (TMR2 register) 8-bit period register (PR2) Readable and writable (both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16 by 1’s) • Interrupt on TMR2 match with PR2 Timer2 has a control register shown in Register 7-1.
PIC16F785/HV785 7.2 Timer2 Interrupt The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon Reset.
PIC16F785/HV785 8.0 CAPTURE/COMPARE/PWM (CCP) MODULE TABLE 8-1: The Capture/Compare/PWM (CCP) module contains a 16-bit register which can operate as a: • 16-bit Capture register • 16-bit Compare register • PWM Master/Slave Duty Cycle register CCP MODE – TIMER RESOURCES REQUIRED CCP Mode Timer Resource Capture Timer1 Compare Timer1 PWM Timer2 Capture/Compare/PWM Register 1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte).
PIC16F785/HV785 8.1 8.1.4 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC5/CCP1. An event is defined as one of the following and is configured by CCP1CON<3:0>: • • • • Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge When a capture is made, the interrupt request flag bit CCP1IF of the PIR1 Register is set. The interrupt flag must be cleared in software.
PIC16F785/HV785 8.2.1 CCP1 PIN CONFIGURATION 8.2.4 The user must configure the RC5/CCP1 pin as an output by clearing the TRISC<5> bit. Note: 8.2.2 In this mode (CCP1M<3:0> = 1011), an internal hardware trigger is generated, which may be used to initiate an action. See Register 8-1. Clearing the CCP1CON register will force the RC5/CCP1 compare output latch to the default low level. This is not the PORTC I/O data latch.
PIC16F785/HV785 8.3 8.3.1 CCP PWM Mode In Pulse Width Modulation (PWM) mode, the CCP module produces up to a 10-bit resolution PWM output on the RC5/CCP1 pin. Since the RC5/CCP1 pin is multiplexed with the PORTC data latch, the TRISC<5> must be cleared to make the RC5/CCP1 pin an output. Note: Clearing the CCP1CON register will force the PWM output latch to the default inactive levels. This is not the PORTC I/O data latch. Figure 8-3 shows a simplified block diagram of PWM operation.
PIC16F785/HV785 8.3.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the DC1B<1:0> bits of the CCP1CON register. Up to 10 bits of resolution is available. The CCPR1L contains the eight MSbs and the DC1B<1:0> contains the two LSbs. In PWM mode, CCPR1H is a read-only register. Equation 8-2 is used to calculate the PWM duty cycle in time.
PIC16F785/HV785 8.3.3 OPERATION IN SLEEP MODE 8.3.5 In Sleep mode, all clock sources are disabled. Timer2 will not increment and the state of the module will not change. If the RC5/CCP1 pin is driving a value, it will continue to drive that value. When the device wakes up, it will continue from this state. 8.3.3.
PIC16F785/HV785 9.0 COMPARATOR MODULE The Comparator module has two separate voltage comparators: Comparator 1 (C1) and Comparator 2 (C2).
PIC16F785/HV785 FIGURE 9-1: COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM C1CH<1:0> C1POL 2 D RA1/AN1/C12IN0-/VREF/ICSPCLK RC1/AN5/C12IN1-/PH1 Q1 0 RC2/AN6/C12IN2-/OP2 1 MUX 2 RC3/AN7/C12IN3-/OP1 3 Q EN To Data Bus RD_CM1CON0 Set C1IF D Q Q3*RD_CM1CON0 C1ON(1) C1R EN CL NRESET To PWM Logic C1OE C1SP C1VN RA0/AN0/C1IN+/ICSPDAT C1VREF 0 MUX 1 C1OUT C1VP C1 RA2/AN2/T0CKI/INT/C1OUT(2) C1POL Note 1: 2: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate.
PIC16F785/HV785 REGISTER 9-1: CM1CON0: COMPARATOR C1 CONTROL REGISTER 0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 C1ON: Comparator C1 Enable bit 1 = C1 Comparator is enabled 0 = C1 Comparator is disabled bit 6 C1OUT: Comparator C1 Output bit If C1POL = 1 (inverted polarity): C1OUT = 1
PIC16F785/HV785 9.1.2 COMPARATOR C2 CONTROL REGISTERS The comparator output, C2OUT, can be inverted by setting the C2POL bit of the CM2CON0 Register. Clearing C2POL results in a non-inverted output. The CM2CON0 register is a functional copy of the CM1CON0 register described in Section 9.1.1 “Comparator C1 Control Register”. A second control register, CM2CON1, is also present for control of an additional synchronizing feature, as well as mirrors of both comparator outputs.
PIC16F785/HV785 REGISTER 9-2: CM2CON0: COMPARATOR C2 CONTROL REGISTER 0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 C2ON: Comparator C2 Enable bit 1 = C2 Comparator is enabled 0 = C2 Comparator is disabled bit 6 C2OUT: Comparator C2 Output bit If C2POL = 1 (inverted polarity): C2OUT = 1
PIC16F785/HV785 9.1.2.2 Control Register CM2CON1 Comparator C2 has one additional feature: its output can be synchronized to the Timer1 clock input. Setting C2SYNC of the CM2CON1 Register synchronizes the output of Comparator 2 to the falling edge of the Timer1 clock input (see Figure 9-2 and Register 9-3). The CM2CON1 register also contains mirror copies of both comparator outputs, MC1OUT and MC2OUT of the CM2CON1 Register.
PIC16F785/HV785 9.2 Comparator Outputs The comparator outputs are read through the CM1CON0, COM2CON0 or CM2CON1 registers. CM1CON0 and CM2CON0 each contain the individual comparator output of Comparator 1 and Comparator 2, respectively. CM2CON2 contains a mirror copy of both comparator outputs facilitating a simultaneous read of both comparators. These bits are read-only. The comparator outputs may also be directly output to the RA2/AN2/T0CKI/INT/C1OUT and RC4/C2OUT/PH2 I/O pins.
PIC16F785/HV785 10.0 VOLTAGE REFERENCES There are two voltage references available in the PIC16F785/HV785: The voltage referred to as the comparator reference (CVREF) is a variable voltage based on VDD; The voltage referred to as the VR reference (VR) is a fixed voltage derived from a stable band gap source. Each source may be individually routed internally to the comparators or output, buffered or unbuffered, on the RA1/AN1/C12IN0-/VREF/ICSPCLK pin. 10.
PIC16F785/HV785 FIGURE 10-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM 16 Stages 8R R R R R VDD 8R VRR 16-1 Analog MUX CVREN(1) 15 CVREF · · · 0 VR3:VR0 CVROE C1VREN C1VREF to Comparator 1 Input 1 0 C2VREN C2VREF to Comparator 2 Input 1 0 VR 1.2 V Note 1: See Register 10-1, bits 3-0. © 2008 Microchip Technology Inc.
PIC16F785/HV785 REGISTER 10-1: R/W-0 VRCON: VOLTAGE REFERENCE CONTROL REGISTER R/W-0 (1) C1VREN (1) C2VREN R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 VRR — VR3 VR2 VR1 VR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 C1VREN: Comparator 1 Voltage Reference Enable bit(1) 1 = CVREF circuit powered on and routed to C1VREF input of comparator 1 0 = 1.
PIC16F785/HV785 10.2 VR Reference Module The VR Reference module generates a 1.2V nominal output voltage for use by the ADC and comparators. The output voltage can also be brought out to the VREF pin for user applications. This module uses a bandgap as a reference. See Table 19-9 for detailed specifications. Register 10-2 shows the control register for the VR module.
PIC16F785/HV785 10.2.1 VR STABILIZATION PERIOD When the Voltage Reference module is enabled, it will require some time for the reference and its amplifier circuits to stabilize. The user program must include a small delay routine to allow the module to settle. See Section 19.0 “Electrical Specifications” for the minimum delay requirement.
PIC16F785/HV785 11.0 OPERATIONAL AMPLIFIER (OPA) MODULE 11.2 The OPA module is enabled by setting the OPAON bit of the OPAxCON Register. When enabled, OPAON forces the output driver of RC3/AN7/C12IN3-/OP1 for OPA1, and RC2/AN6/C12IN2-/OP2 for OPA2, into tristate to prevent contention between the driver and the OPA output. The ADC and comparator inputs which share the op amp pins operate normally when the op amp is enabled.
PIC16F785/HV785 REGISTER 11-1: OPA1CON: OP AMP 1 CONTROL REGISTER R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 OPAON — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OPAON: Op Amp Enable bit 1 = Op Amp 1 is enabled 0 = Op Amp 1 is disabled bit 6-0 Unimplemented: Read as ‘0’ REGISTER 11-2: x = Bit is unknown OPA2CON: OP AMP 2 CONTROL REGISTER R/W-0 U-0 U-0 U-0 U-0 U-0
PIC16F785/HV785 11.3 Effects of a Reset Leakage current is a measure of the small source or sink currents on the OPA+ and OPA- inputs. To minimize the effect of leakage currents, the effective impedances connected to the OPA+ and OPA- inputs should be kept as small as possible and equal. A device Reset forces all registers to their Reset state. This disables both op amps. 11.
PIC16F785/HV785 NOTES: DS41249E-page 78 © 2008 Microchip Technology Inc.
PIC16F785/HV785 12.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The analog-to-digital converter (A/D) allows conversion of an analog input signal to a 10-bit binary representation of that signal. The PIC16F785/HV785 has twelve analog I/O inputs, plus two internal inputs, multiplexed into one sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a binary result via successive approximation and stores the result in a 10-bit register.
PIC16F785/HV785 12.1 A/D Configuration and Operation There are four registers available to control the functionality of the A/D module: 1. 2. 3. 4. ANSEL0 (Register 12-1) ANSEL1 (Register 12-2) ADCON0 (Register 12-3) ADCON1 (Register 12-4) 12.1.1 The ANS<11:0> bits, of the ANSEL1 and ANSEL0 Registers, and the TRISA<4,2:0>, TRISB<5:4> and TRISC<7:6,3:0>> bits control the operation of the A/D port pins. Set the corresponding TRISx bits to ‘1’ to set the pin output driver to its high-impedance state.
PIC16F785/HV785 12.1.5 STARTING A CONVERSION If the conversion must be aborted, the GO/DONE bit can be cleared in software. The ADRESH:ADRESL registers will not be updated with the partially complete A/D conversion sample. Instead, the ADRESH:ADRESL registers will retain the value of the previous conversion. After an aborted conversion, a 2 TAD delay is required before another acquisition can be initiated. Following the delay, an input acquisition is automatically started on the selected channel.
PIC16F785/HV785 REGISTER 12-1: ANSEL0: ANALOG SELECT REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown ANS<7:0>: Analog Select bits Analog select between analog or digital function on pins AN<7:0>, respectively. 1 = Analog input. Pin is assigned as analog input.
PIC16F785/HV785 REGISTER 12-3: ADCON0: A/D CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM VCFG CHS3 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ADFM: A/D Result Formed Select bit 1 = Right justified 0 = Left justified bit 6 VCFG: Voltage Reference bit 1 = VREF pin 0 = VDD bit 5-2 CHS<3:0>: Analog Chann
PIC16F785/HV785 REGISTER 12-4: ADCON1: A/D CONTROL REGISTER 1 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — ADCS2 ADCS1 ADCS0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 x11 = FRC (clock derived from a dedicated internal oscillator = 5
PIC16F785/HV785 12.1.7 CONFIGURING THE A/D After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as inputs. To determine sample time, see Table 19-16 and Table 19-17. After this sample time has elapsed, the A/D conversion can be started. These steps should be followed for an A/D conversion: 1. 2. 3. 4. 5. 6. 7.
PIC16F785/HV785 12.2 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 12-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 12-4.
PIC16F785/HV785 FIGURE 12-4: ANALOG INPUT MODEL VDD RS ANx CPIN 5 pF VA VT = 0.6V VT = 0.6V RIC ≤ 1k Sampling Switch SS RSS CHOLD = DAC capacitance = 10 pF ILEAKAGE ± 500 nA VSS 6V 5V VDD 4V 3V 2V Legend: CPIN = VT = I LEAKAGE = RIC = SS = CHOLD = Input Capacitance Threshold Voltage Leakage current at the pin due to various junctions Interconnect Resistance Sampling Switch Sample/Hold Capacitance (from DAC) © 2008 Microchip Technology Inc.
PIC16F785/HV785 12.3 A/D Operation During Sleep The A/D Converter module can operate during Sleep. This requires the A/D clock source to be set to the FRC option. When the RC clock source is selected, the A/D waits one instruction before starting the conversion. This allows the SLEEP instruction to be executed, thus eliminating much of the switching noise from the conversion. When the conversion is complete, the GO/ DONE bit is cleared and the result is loaded into the ADRESH:ADRESL registers.
PIC16F785/HV785 12.4 Effects of Reset The appropriate analog input channel must be selected and the minimum acquisition done before the “special event trigger” sets the GO/DONE bit (starts a conversion). A device Reset forces all registers to their Reset state. Thus, the A/D module is turned off and any pending conversion is aborted. The ADRESH:ADRESL registers are unchanged. 12.
PIC16F785/HV785 NOTES: DS41249E-page 90 © 2008 Microchip Technology Inc.
PIC16F785/HV785 13.0 TWO-PHASE PWM EQUATION 13-2: The two-phase PWM (Pulse Width Modulator) is a stand-alone peripheral that supports: • Single or dual-phase PWM • Single complementary output PWM with overlap/ delay • Sync input/output to cascade devices for additional phases Setting either, or both, of the PH1EN or PH2EN bits of the PWMCON0 register will activate the PWM module (see Register 13-1). If PH1 is used then TRISC<1> must be cleared to configure the pin as an output.
PIC16F785/HV785 13.5 Active PWM Output Level The PWMASE bit (see Register 13-2) is set by hardware when a shutdown event occurs. If automatic restarts are not enabled (PRSEN = 0, see Register 13-1), PWM operation will not resume until the PWMASE bit is cleared by firmware after the shutdown condition clears. The PWMASE bit can not be cleared as long as the shutdown condition exists. If automatic restarts are not enabled, the auto-shutdown mode can be forced by writing a ‘1’ to the PWMASE bit.
PIC16F785/HV785 REGISTER 13-1: PWMCON0: PWM CONTROL REGISTER 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRSEN PASEN BLANK2 BLANK1 SYNC1 SYNC0 PH2EN PH1EN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the PWMASE shutdown bit clears automatically once the shutdown condition goes away.
PIC16F785/HV785 REGISTER 13-2: PWMCLK: PWM CLOCK CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PWMASE PWMP1 PWMP0 PER4 PER3 PER2 PER1 PER0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PWMASE: PWM Auto-Shutdown Event Status bit 0 = PWM outputs are operating 1 = A shutdown event has occured. PWM outputs are inactive.
PIC16F785/HV785 REGISTER 13-3: PWMPH1: PWM PHASE 1 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 POL C2EN C1EN PH4 PH3 PH2 PH1 PH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 POL: PH1 Output Polarity bit 1 = PH1 Pin is active-low 0 = PH1 Pin is active-high bit 6 C2EN: Comparator 2 Enable bit When COMOD<1:0> = 00(1) 1 = PH1 is reset whe
PIC16F785/HV785 REGISTER 13-4: PWMPH2: PWM PHASE 2 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 POL C2EN C1EN PH4 PH3 PH2 PH1 PH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 POL: PH2 Output Polarity bit 1 = PH2 Pin is active low 0 = PH2 Pin is active high bit 6 C2EN: Comparator 2 Enable bit When COMOD<1:0> = 00(1) 1 = PH2 is reset whe
PIC16F785/HV785 FIGURE 13-2: TWO-PHASE PWM AUTO-SHUTDOWN AND SYNC TIMING FOSC PWMP<1:0> = 0X01, PER<4:0> = 0X03 MASTER pwm_clk pwm_count 0 1 2 0 1 2 1 2 3 0 1 2 1 2 3 0 SYNC Phase1 setup: PH<4:0> = 0x00, C1EN = 1, BLANK1 = 0 pha1 SHUTDOWN SLAVE pwm_clk pwm_count 0 1 2 0 3 0 3 0 Phase2 setup: PH<4:0> = 0x02, C2EN = 1, BLANK2 = 1 pha2 FIGURE 13-3: TWO-PHASE PWM START-UP TIMING FOSC PWMP<1:0> = 0X01, PER<4:0> = 0X03 MASTER pwm_clk pwm_count 0 1 2 0 1 2 3 0 1 2 0
PIC16F785/HV785 13.7 Example Single Phase Application Figure 13-4 shows an example of a single phase buck voltage regulator application. The PWM output drives Q1 with pulses to alternately charge and discharge L1. C4 holds the charge from L1 during the inactive cycle of the drive period. R4 and C3 form a ramp generator. At the beginning of the PWM period, the PWM output goes high causing the voltage on C3 to rise concurrently with the current in L1.
PIC16F785/HV785 13.8 PWM Configuration When configuring the Two-Phase PWM, care must be taken to avoid active output levels from the PH1 and PH2 pins before the PWM is fully configured. The following sequence is suggested before the TRISC register or any of the Two-Phase PWM control registers are first configured: • Output inactive (OFF) levels to the PORTC RC1/ AN5/C12IN1-/PH1 and RC4/C2OUT/PH2 pins. • Clear TRISC bits 1 and 4 to configure the PH1 and PH2 pins as outputs.
PIC16F785/HV785 13.9 Complementary Output Mode The Two-Phase PWM module may be configured to operate in a Complementary Output mode where PH1 and PH2 are always 180 degrees out-of-phase (see Figure 13-5). Three complementary modes are available and are selected by the COMOD<1:0> bits in the PWMCON1 register (see Register 13-5). The difference between the modes is the method by which the PH1 and PH2 outputs switch from the active to the inactive state during the PWM period.
PIC16F785/HV785 REGISTER 13-5: PWMCON1: PWM CONTROL REGISTER 1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — COMOD1 COMOD0 CMDLY4 CMDLY3 CMDLY2 CMDLY1 CMDLY0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-5 COMOD<1:0>: Complementary Mode Select bits(1) 00 = Normal two-phase operation. Complementary mode is disabled.
PIC16F785/HV785 FIGURE 13-6: COMPLEMENTARY OUTPUT PWM TIMING FOSC PWMP<1:0> = 0X01, PER<4:0> = 0X03 pwm_clk 3 pwm_count 0 2 1 3 0 1 0 2 1 3 0 1 SYNC C1OUT Phase 1 setup: PH<4:0> = 0x00, C1EN = 1, BLANKx = X, COMOD<1:0> = 0x01 pha1 pha2 Delay Delay Shutdown TABLE 13-1: REGISTERS/BITS ASSOCIATED WITH PWM Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0 0000 0000 0000 000
PIC16F785/HV785 14.0 DATA EEPROM MEMORY The EEPROM data memory is readable and writable during normal operation (full VDD range). This memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers. There are four SFRs used to read and write this memory: • • • • EECON1 EECON2 (not a physically implemented register) EEDAT EEADR EEDAT holds the 8-bit data for read/write, and EEADR holds the address of the EEPROM location being accessed.
PIC16F785/HV785 14.1 EECON1 and EECON2 Registers EECON1 is the control register with four low-order bits physically implemented. The upper four bits are nonimplemented and read as ‘0’s. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set in software. They are cleared in hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation.
PIC16F785/HV785 14.2 Reading the EEPROM Data Memory To read a data memory location, the user must write the address to the EEADR register and then set control bit RD of the EECON1 Register, as shown in Example 141. The data is available, in the very next cycle, in the EEDAT register. Therefore, it can be read in the next instruction. EEDAT holds this value until another read, or until it is written to by the user (during a write operation). EXAMPLE 14-1: BSF BCF MOVLW MOVWF BSF MOVF 14.
PIC16F785/HV785 14.6 Data EEPROM Operation During Code-Protect Data memory can be code-protected by programming the CPD bit in the Configuration Word (Register 15.2) to ‘0’. When the data memory is code-protected, the CPU is able to read and write data to the data EEPROM. It is recommended that the user code protect the program memory when code protecting the data memory.
PIC16F785/HV785 15.0 SPECIAL FEATURES OF THE CPU The PIC16F785/HV785 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving features and offer code protection.
PIC16F785/HV785 REGISTER 15-1: CONFIG: CONFIGURATION WORD U-0 U-0 U-0 U-0 R/P-0 R/P-0 R/P-1 R/P-1 — — — — FCMEN IESO BOREN1 BOREN0 bit 15 bit 8 R/P-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 13-12 FCMEN: Fail-Safe Clock Monitor Enabled bit(5) 1 = Fail-Safe
PIC16F785/HV785 15.2 Reset The PIC16F785/HV785 differentiates between various kinds of Reset: • • • • • • Power-on Reset (POR) WDT Reset during normal operation WDT Reset during Sleep MCLR Reset during normal operation MCLR Reset during Sleep Brown-out Reset (BOR) Some registers are not affected in any Reset condition; their status is unknown on POR and unchanged in any other Reset.
PIC16F785/HV785 15.2.1 POWER-ON RESET The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation. A minimum rise rate for VDD is required. See Section 19.0 “Electrical Specifications” for details. If the BOR is enabled, the minimum rise rate specification does not apply. The BOR circuitry will keep the device in Reset until VDD reaches VBOR (see Section 15.2.4 “Brown-Out Reset (BOR)”) The POR circuit, on this device, has a POR re-arm circuit.
PIC16F785/HV785 15.2.5 BOR CALIBRATION The PIC16F785/HV785 stores the BOR calibration values in fuses located in the Calibration Word (2008h). The Calibration Word is not erased when using the specified bulk erase sequence in the “PIC16F785/ HV785 Memory Programming Specification” (DS41237) and thus, does not require reprogramming. Note: Address 2008h is beyond the user program memory space. It belongs to the special configuration memory space (2000h3FFFh), which can be accessed only during programming.
PIC16F785/HV785 15.2.6 TIME-OUT SEQUENCE 15.2.7 On power-up, the time-out sequence is as follows: first, PWRT time out is invoked after POR has expired, then OST is activated after the PWRT time out has expired. The total time out will vary based on oscillator configuration and PWRTE bit status. For example, in EC mode with PWRTE bit equal to ‘1’ (PWRT disabled), there will be no time out at all. Figure 15-4, Figure 15-6 and Figure 15-6 depict time-out sequences.
PIC16F785/HV785 FIGURE 15-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2 FIGURE 15-5: VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 15-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD) VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset © 2008 Microchip Technology Inc.
PIC16F785/HV785 TABLE 15-4: INITIALIZATION CONDITION FOR REGISTERS Register W INDF TMR0 Address Power-on Reset MCLR Reset WDT Reset Brown-out Reset(1) Wake-up from Sleep through interrupt Wake-up from Sleep through WDT Time-out — xxxx xxxx uuuu uuuu uuuu uuuu 00h/80h xxxx xxxx xxxx xxxx uuuu uuuu 01h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h/82h 0000 0000 0000 0000 PC + 1(3) STATUS 03h/83h 0001 1xxx 000q quuu(4) uuuq quuu(4) FSR 04h/84h xxxx xxxx uuuu uuuu uuuu uuuu (6) (7) -
PIC16F785/HV785 TABLE 15-4: Register VRCON INITIALIZATION CONDITION FOR REGISTERS (CONTINUED) Address Power-on Reset MCLR Reset WDT Reset Brown-out Reset(1) Wake-up from Sleep through interrupt Wake-up from Sleep through WDT Time-out 99h 000- 0000 000- 0000 uuu- uuuu EEDAT 9Ah 0000 0000 0000 0000 uuuu uuuu EEADR 9Bh 0000 0000 0000 0000 uuuu uuuu EECON1 9Ch ---- x000 ---- q000 ---- uuuu EECON2 9Dh ---- ---- ---- ---- ---- ---- ADRESL 9Eh xxxx xxxx uuuu uuuu uuuu uuuu ADCON1
PIC16F785/HV785 TABLE 15-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS Program Counter STATUS Register PCON Register Power-on Reset 000h 0001 1xxx ---1 --0x MCLR Reset during normal operation 000h 000u uuuu ---u --uu MCLR Reset during Sleep 000h 0001 0uuu ---u --uu Condition WDT Reset WDT Wake-up Brown-out Reset Interrupt Wake-up from Sleep 000h 0000 uuuu ---u --uu PC + 1 uuu0 0uuu ---u --uu 000h 0001 1uuu ---1 --u0 PC + 1(1) uuu1 0uuu ---u --uu Legend: u = unchanged, x = u
PIC16F785/HV785 15.3 Interrupts The PIC16F785/HV785 has 11 sources of interrupt: • • • • • • • • • • External Interrupt RA2/INT TMR0 Overflow Interrupt PORTA Change Interrupt 2 Comparator Interrupts A/D Interrupt Timer1 Overflow Interrupt Timer2 Match Interrupt EEPROM Data Write Interrupt Fail-Safe Clock Monitor Interrupt CCP Interrupt The Interrupt Control register (INTCON) and Peripheral Interrupt register (PIR1) record individual interrupt requests in flag bits.
PIC16F785/HV785 15.3.1 RA2/AN2/T0CKI/INT/C1OUT INTERRUPT 15.3.2 External interrupt on RA2/AN2/T0CKI/INT/C1OUT pin is edge-triggered; either rising, if INTEDG bit of the OPTION Register is set, or falling, if INTEDG bit is clear. When a valid edge appears on the RA2/AN2/ T0CKI/INT/C1OUT pin, the INTF bit of the INTCON Register is set. This interrupt can be disabled by clearing the INTE control bit of the INTCON Register.
PIC16F785/HV785 FIGURE 15-8: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT(3) (4) INT pin (1) (1) INTF Flag (INTCON<1>) Interrupt Latency (2) (5) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Inst (PC) Instruction Executed Inst (PC - 1) Note 1: 2: 3: 4: 5: Inst (0004h) Inst (0005h) Dummy Cycle Inst (0004h) — Inst (PC + 1) Dummy Cycle Inst (PC) 0005h INTF flag is sampled here (every Q1).
PIC16F785/HV785 15.4 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W and STATUS registers). This must be implemented in software. Since the last 16 bytes of all banks are common in the PIC16F785/HV785 (see Figure 2-2), temporary holding registers W_TEMP and STATUS_TEMP should be placed in here.
PIC16F785/HV785 15.5 15.5.2 Watchdog Timer (WDT) For PIC16F785/HV785, the WDT has been modified from previous PIC16FXXX devices. The new WDT is code and functionally compatible with previous PIC16FXXX WDT modules and adds a 16-bit prescaler to the WDT. This allows the user to scale the value for the WDT and TMR0 at the same time. In addition, the WDT time out value can be extended to 268 seconds. WDT is cleared under certain conditions described in Table 15-7. 15.5.
PIC16F785/HV785 REGISTER 15-2: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS<3:0>: Watchdog Timer Period Select bits Bit Value = Prescale Rate 0000 = 1:32 0001 = 1:64 0010 = 1:128 0011 = 1:256 0100 = 1:512 (Re
PIC16F785/HV785 15.6 Power-Down Mode (Sleep) The Power-down mode is entered by executing a SLEEP instruction. If the Watchdog Timer is enabled: • • • • • WDT will be cleared but keeps running PD bit in the STATUS register is cleared TO bit is set Oscillator driver is turned off I/O ports maintain the status they had before SLEEP was executed (driving high, low or highimpedance).
PIC16F785/HV785 FIGURE 15-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT(1) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKOUT(4) INT pin INTF flag (INTCON<1>) Interrupt Latency (3) GIE bit (INTCON<7>) Processor in Sleep INSTRUCTION FLOW PC PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: 15.7 Inst(PC) = Sleep Inst(PC - 1) PC + 1 PC + 2 Inst(PC + 1) Inst(PC + 2) Sleep Inst(PC + 1) 15.
PIC16F785/HV785 TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION To Normal Connections External Connector Signals * FIGURE 15-12: PIC16F785 +5.0V VDD 0V VSS VPP MCLR/VPP/RA3 CLK RA1 Data I/O RA0 * * For more information, see “MPLAB® ICD 2 In-Circuit Debugger User’s Guide” (DS51331), available on Microchip’s web site (www.microchip.com).
PIC16F785/HV785 16.0 VOLTAGE REGULATOR The PIC16HV785 includes a permanent internal 5 volt (nominal) shunt regulator in parallel with the VDD pin. This eliminates the need for an external voltage regulator in systems sourced by an unregulated supply. All external devices connected directly to the VDD pin will share the regulated supply voltage and contribute to the total VDD supply current (ILOAD). 16.
PIC16F785/HV785 17.0 INSTRUCTION SET SUMMARY The PIC16F785/HV785 instruction set is highly orthogonal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction.
PIC16F785/HV785 TABLE 17-2: PIC16F785/HV785 INSTRUCTION SET Mnemonic, Operands 14-Bit Opcode Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f – f, d f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f
PIC16F785/HV785 17.2 Instruction Descriptions ADDLW Add Literal and W ANDWF AND W with f Syntax: [label] ADDLW Syntax: [label] ANDWF Operands: 0 ≤ k ≤ 255 Operands: Operation: (W) + k → (W) 0 ≤ f ≤ 127 d ∈ [0,1] Status Affected: C, DC, Z Operation: (W) .AND. (f) → (destination) Description: The contents of the W register are added to the eight-bit literal ‘k’ and the result is placed in the W register. Status Affected: Z Description: AND the W register with register ‘f’.
PIC16F785/HV785 BTFSC Bit Test f, Skip if Clear CLRF Clear f Syntax: [label] BTFSC f,b Syntax: [label] CLRF Operands: 0 ≤ f ≤ 127 0≤b≤7 Operands: 0 ≤ f ≤ 127 Operation: skip if (f) = 0 Operation: 00h → (f) 1→Z Status Affected: None Status Affected: Z Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed. If bit ‘b’, in register ‘f’, is ‘0’, the next instruction is discarded, and a NOP is executed instead, making this a two-cycle instruction.
PIC16F785/HV785 GOTO Unconditional Branch Syntax: [ label ] Operands: 0 ≤ k ≤ 2047 Operation: k → PC<10:0> PCLATH<4:3> → PC<12:11> Z Status Affected: None Description: The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. Description: GOTO is an unconditional branch. The eleven-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>.
PIC16F785/HV785 IORLW Inclusive OR Literal with W MOVLW Move Literal to W Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ k ≤ 255 Operation: (W) .OR. k → (W) Operation: k → (W) Status Affected: Z Status Affected: None Description: The contents of the W register are OR’ed with the eight-bit literal ‘k’. The result is placed in the W register. Encoding: IORLW k 11 MOVLW k 00xx kkkk kkkk Description: The eight-bit literal ‘k’ is loaded into W register.
PIC16F785/HV785 RETFIE Return from Interrupt RLF Rotate Left f through Carry Syntax: [ label ] Syntax: [ label ] Operands: None Operands: Operation: TOS → PC, 1 → GIE 0 ≤ f ≤ 127 d ∈ [0,1] Operation: See description below None Status Affected: C Status Affected: Encoding: Description: RETLW 00 RETFIE 0000 0000 1001 Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC.
PIC16F785/HV785 SUBLW Subtract W from Literal Syntax: [label] Operands: Operation: Status Affected: TRIS Load TRIS Register Syntax: [ label ] TRIS 0 ≤ k ≤ 255 Operands: 5≤f≤6 k - (W) → (W) Operation: (W) → TRIS register f; C, DC, Z Status Affected: None Encoding: 00 Description: The instruction is supported for code compatibility with the PIC16C5X products. Since TRIS registers are readable and writable, the user can directly address them.
PIC16F785/HV785 XORWF Exclusive OR W with f Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) .XOR. (f) → (dest) Status Affected: Z Encoding: 00 Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’ the result is stored back in register ‘f’. © 2008 Microchip Technology Inc.
PIC16F785/HV785 NOTES: DS41249E-page 136 © 2008 Microchip Technology Inc.
PIC16F785/HV785 18.
PIC16F785/HV785 18.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging.
PIC16F785/HV785 18.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.
PIC16F785/HV785 18.11 PICSTART Plus Development Programmer 18.13 Demonstration, Development and Evaluation Boards The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins.
PIC16F785/HV785 19.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias................................................................................................................. -40 to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS ...............................................................................
PIC16F785/HV785 FIGURE 19-1: PIC16F785/HV785 WITH ANALOG DISABLED VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C(2) 5.5 (3) 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 8 10 12 Frequency 16 20 (MHz)(2) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Frequency denotes system clock frequency. When using the HFINTOSC the system clock is after the postscaler. 3: The internal shunt regulator of the PIC16HV785 keeps VDD at or below 5.0V (nominal).
PIC16F785/HV785 19.1 DC Characteristics: PIC16F785/HV785-I (Industrial), PIC16F785/HV785-E (Extended) DC CHARACTERISTICS Param No. Sym VDD Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Min Typ† Max Units 2.0 2.2 2.5 3.0 4.5 — — — — — 5.5 5.5 5.5 5.5 5.
PIC16F785/HV785 DC Characteristics: PIC16F785/HV785-I (Industrial)(1), (2) 19.2 DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Conditions Param No. Device Characteristics Min Typ† Max Units VDD D010 Supply Current (IDD) D011 D012 D013 D014 D015 D016 D017 D018 † Note 1: 2: 3: 4: — 11 23 μA 2.0 — 18 38 μA 3.0 — 35 75 μA 5.0 — 140 240 μA 2.0 — 220 380 μA 3.0 — 380 550 μA 5.
PIC16F785/HV785 DC Characteristics: PIC16F785/HV785-I (Industrial)(1), (2) (Continued) 19.2 DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Conditions Param No. Device Characteristics Min Typ† Max Units — 0.15 1.2 μA 2.0 — 0.20 1.5 μA 3.0 — 0.35 1.8 μA 5.0 — 1.7 3.0 μA 2.0 — 2 4 μA 3.0 VDD D020 Power-down Base Current (IPD)(4) D021 — 3 7 μA 5.0 D022 — 42 60 μA 3.
PIC16F785/HV785 DC Characteristics: PIC16F785/HV785-E (Extended)(1), (2) 19.3 DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C for extended Conditions Param No. Device Characteristics Min Typ† Max Units VDD D010E Supply Current (IDD) D011E D012E D013E D014E D015E D016E D017E D018E † Note 1: 2: 3: 4: — 11 23 μA 2.0 — 18 38 μA 3.0 — 35 75 μA 5.0 — 140 240 μA 2.0 — 220 380 μA 3.
PIC16F785/HV785 DC Characteristics: PIC16F785/HV785-E (Extended)(1), (2) (Continued) 19.3 DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C for extended Conditions Param No. Device Characteristics Min Typ† Max Units — 0.15 9 μA 2.0 — 0.20 11 μA 3.0 — 0.35 15 μA 5.0 — 1.7 17.5 μA 2.0 — 2 19 μA 3.0 VDD D020E Power-down Base Current (IPD)(4) D021E — 3 22 μA 5.0 D022E — 42 65 μA 3.
PIC16F785/HV785 19.4 DC Characteristics: PIC16F785/HV785-I (Industrial), PIC16F785/HV785-E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature-40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended DC CHARACTERISTICS Param No. Sym VIL Characteristic Min Typ† Max Units VSS VSS Conditions — 0.8 V 4.5V ≤ VDD ≤ 5.5V — 0.15 VDD V Otherwise VSS — 0.2 VDD V Entire range VSS — 0.
PIC16F785/HV785 19.4 DC Characteristics: PIC16F785/HV785-I (Industrial), PIC16F785/HV785-E (Extended) (Continued) DC CHARACTERISTICS Param No.
PIC16F785/HV785 19.5 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2.
PIC16F785/HV785 FIGURE 19-3: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKOUT TABLE 19-1: Param No. Sym FOSC EXTERNAL CLOCK TIMING REQUIREMENTS Characteristic Min Typ† Max Units External CLKIN Frequency(1) — 32.768 — kHz DC DC DC — — DC 0.1 1 — — — — 32.768 4 — — — 0.
PIC16F785/HV785 FIGURE 19-4: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 22 23 CLKOUT 13 12 19 14 18 16 I/O pin (Input) 15 17 I/O pin (Output) New Value Old Value 20, 21 TABLE 19-2: Param No.
PIC16F785/HV785 TABLE 19-3: Param No. F10 F14 Sym FOSC PRECISION INTERNAL OSCILLATOR PARAMETERS Characteristic Internal Calibrated INTOSC Frequency(1) TIOSCST Oscillator wake-up from Sleep start-up time* Freq. Min Tolerance Typ† Max Units Conditions ±1% 7.92 8.00 8.08 MHz VDD = 3.5V, 25°C ±2% 7.84 8.00 8.16 MHz 2.5V ≤ VDD ≤ 5.5V 0°C ≤ TA ≤ +85°C ±5% 7.60 8.00 8.40 MHz 2.0V ≤ VDD ≤ 5.5V -40°C ≤ TA ≤ +85°C (Ind.) -40°C ≤ TA ≤ +125°C (Ext.) — — 12 24 μs VDD = 2.
PIC16F785/HV785 FIGURE 19-6: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR (Device not in Brown-out Reset) (Device in Brown-out Reset) 36 Reset (due to BOR) Note 1: 64 ms delay only if PWRTE bit in Configuration Word is programmed to ‘0’. TABLE 19-4: Param No.
PIC16F785/HV785 FIGURE 19-7: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 49 47 TMR0 or TMR1 TABLE 19-5: Param No.
PIC16F785/HV785 FIGURE 19-8: CAPTURE/COMPARE/PWM TIMINGS (CCP) CCP1 (Capture mode) 50 51 52 CCP1 (Compare or PWM mode) 53 54 Note: Refer to Figure 19-2 for load conditions. TABLE 19-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP) Param Symbol No. 50* TCCL Characteristic CCP1 input low time Min No Prescaler With Prescaler 51* TCCH CCP1 input high time No Prescaler With Prescaler Typ† Max Units 0.5TCY + 20 — — ns 20 — — ns 0.
PIC16F785/HV785 TABLE 19-7: COMPARATOR SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Comparator Specifications Param No. C01 Symbol Characteristics VOS Input Offset Voltage Min Typ Max Units — ±5 ±10 mV Comments C02 VCM Input Common Mode Voltage 0 — VDD – 1.
PIC16F785/HV785 TABLE 19-11: OPERATIONAL AMPLIFIER (OPA) MODULE DC SPECIFICATIONS OPA DC CHARACTERISTICS Param No. Sym Characteristics Standard Operating Conditions (unless otherwise stated) VCM = 0V, VOUT = VDD/2, VDD = 5.
PIC16F785/HV785 TABLE 19-14: SHUNT REGULATOR SPECIFICATIONS (PIC16HV785 only) SHUNT REGULATOR CHARACTERISTICS Param No. Symbol Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Characteristics VSHUNT Shunt Voltage SR01 SR02 ISHUNT SR03* TSETTLE Settling Time SR04* CLOAD Load Capacitance SR05* ΔISNT Regulator operating current * Min Typ Max Units 4.75 5 5.25 V Shunt Current Comments 4 — 50 mA — — 150 ns To 1% of final value 0.
PIC16F785/HV785 FIGURE 19-9: PIC16F785/HV785 A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO 134 1 TCY (TOSC/2)(1) 131 Q4 130 A/D CLK 9 A/D DATA 8 7 3 6 2 1 0 NEW_DATA OLD_DATA ADRES 1 TCY ADIF GO DONE Note 1: SAMPLING STOPPED 132 SAMPLE If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 19-16: PIC16F785/HV785 A/D CONVERSION REQUIREMENTS Param No.
PIC16F785/HV785 FIGURE 19-10: PIC16F785/HV785 A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO 134 (TOSC/2 + TCY)(1) 1 TCY 131 Q4 130 A/D CLK 9 A/D DATA 8 7 3 6 2 1 NEW_DATA OLD_DATA ADRES 0 ADIF 1 TCY GO DONE Note 1: SAMPLING STOPPED 132 SAMPLE If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 19-17: PIC16F785/HV785 A/D CONVERSION REQUIREMENTS (SLEEP MODE) Param No.
PIC16F785/HV785 NOTES: DS41249E-page 162 © 2008 Microchip Technology Inc.
PIC16F785/HV785 20.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range.
PIC16F785/HV785 FIGURE 20-2: MAXIMUM IDD vs. FOSC OVER VDD (EC MODE) 4.0 3.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 5.5V 5.0V 3.0 IDD (mA) 2.5 4.0V 2.0 3.0V 1.5 2.0V 1.0 0.5 0.0 1 MHz 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz FOSC FIGURE 20-3: TYPICAL IDD vs. FOSC OVER VDD (HS MODE) HS Mode 4.0 3.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 5.5V 3.0 5.0V IDD (mA) 2.
PIC16F785/HV785 FIGURE 20-4: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE) HS Mode 5.0 4.5 4.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 5.5V IDD (mA) 3.5 5.0V 3.0 4.5V 2.5 2.0 1.5 4.0V 3.5V 3.0V 1.0 0.5 0.0 4 MHz 10 MHz 16 MHz 20 MHz FOSC FIGURE 20-5: TYPICAL IDD vs. VDD OVER FOSC (XT MODE) 900 800 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 700 IDD (μA) 600 500 4 MHz 400 300 1 MHz 200 100 0 2.0 2.5 3.
PIC16F785/HV785 FIGURE 20-6: MAXIMUM IDD vs. VDD OVER FOSC (XT MODE) 1,400 1,200 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 1,000 IDD (μA) 800 4 MHz 600 400 1 MHz 200 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 4 4.5 5 5.5 VDD (V) IDD vs. VDD (LP MODE) FIGURE 20-7: 90 Typical Typical Typical: Mean@25×C @25°C Typical:Statistical Statistical Mean 802.0 Maximum: (Worst-case 11Mean Maximum: Mean (Worst Case Temp) + 3σ (-40°C T )to+ 125°C) 3 14.5 702.5 3.
PIC16F785/HV785 FIGURE 20-8: TYPICAL IDD vs. VDD OVER FOSC (EXTRC MODE) 800 700 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 600 IDD (μA) 500 4 MHz 400 300 1 MHz 200 100 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 20-9: MAXIMUM IDD vs. VDD OVER FOSC (EXTRC MODE) 1,400 1,200 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) IDD (μA) 1,000 4 MHz 800 600 1 MHz 400 200 0 2.0 2.5 3.0 3.5 4.0 4.
PIC16F785/HV785 FIGURE 20-10: IDD vs. VDD OVER FOSC (LFINTOSC MODE, 31 kHz) LFINTOSC Mode, 31KHZ 80 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 70 60 IDD (μA) 50 Maximum 40 30 Typical 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 20-11: TYPICAL IDD vs. FOSC OVER VDD (HFINTOSC MODE) 1,600 1,400 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 5.5V 5.0V 1,200 IDD (μA) 1,000 4.0V 800 3.0V 600 2.
PIC16F785/HV785 FIGURE 20-12: MAXIMUM IDD vs. FOSC OVER VDD (HFINTOSC MODE) 2,000 1,800 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 5.5V 5.0V 1,600 1,400 4.0V IDD (μA) 1,200 1,000 3.0V 800 600 2.0V 400 200 0 125 kHz 250 kHz 500 kHz 1 MHz 2 MHz 4 MHz 8 MHz FOSC FIGURE 20-13: TYPICAL IPD vs. VDD (SLEEP yp MODE, ALL PERIPHERALS DISABLED) (Sleep Mode all Periphreals Disabled) 0.50 0.45 Typical: Statistical Mean @25°C 0.40 IPD (uA) 0.35 0.30 0.
PIC16F785/HV785 FIGURE 20-14: MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Maximum (Sleep Mode all Periphreals Disabled) 16.0 14.0 Max 125°C 12.0 10.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) IPD (uA) 8.0 6.0 4.0 Max 85°C 2.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 20-15: COMPARATOR IPD vs.
PIC16F785/HV785 FIGURE 20-16: COMPARATOR IPD vs. VDD (BOTH COMPARATORS ENABLED) CXSP=1 800 700 Typical: Statistical Mean @25°C Typical: Statistical Mean @25×C Maximum: Mean (Worst-case Temp) + 3σ Maximum: Mean (Worst Case (-40°C to 125°C) Temp)+ 3 600 Max IPD (uA) 500 400 Typical 300 200 100 0 2.0 2.5 2 FIGURE 20-17: 3.0 Typical Max 362 4 60 3.5 4.0 4.5 5.0 5.5 VDD (V) BOR IPD vs.
PIC16F785/HV785 FIGURE 20-18: TYPICAL WDT IPD vs. VDD OVER TEMPERATURE 3.5 3.0 IPD (uA) 2.5 2.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ Typical Max 85×C Max 125×C (-40°C to 125°C) 3.000 2 1.700 4.5 2.51.850 3.500 4.75 3 2.000 4.000 5 3.52.250 4.750 6.25 4 2.500 5.500 7.5 4.52.750 6.250 8.75 5 3.000 7.000 10 5.53.250 7.750 1.5 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 20-19: MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE 12.0 10.
PIC16F785/HV785 FIGURE 20-20: CVREF IPD vs. VDD OVER TEMPERATURE (HIGH RANGE) High Range 140 120 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 100 IPD (μA) Max. 125°C 80 Max. 85°C 60 Typical 40 20 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.0 5.5 VDD (V) FIGURE 20-21: CVREF IPD vs. VDD OVER TEMPERATURE (LOW RANGE) 180 160 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 140 120 IPD (μA) Max. 125°C 100 Max.
PIC16F785/HV785 FIGURE 20-22: T1OSC IPD vs. VDD OVER TEMPERATURE (32 kHz) 60.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 50.0 40.0 IPD (uA) Max 125°C 30.0 20.0 2 2.5 3 3.5 4 4.5 5 5.5 2.0 10.0 0.0 Typ 25×C 2.500 2.850 3.200 3.600 4.000 4.400 4.800 5.200 2.5 Max 85×C 7.00 10.50 14.00 18.50 23.00 27.50 32.00 36.50 3.0 Max 85°C Max 125×C 21.00 24.50 28.00 32.25 36.50 Typ 25°C 40.75 45.00 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 20-23: VOL vs.
PIC16F785/HV785 FIGURE 20-24: VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V) 0.45 Typical: Statistical Mean @25°C Typical: Statistical Mean Temp) @25×C+ 3σ Maximum: Mean (Worst-case Maximum: Meas(-40×C + 3 to 125×C) (-40°C to 125°C) 0.40 Max. 125°C 0.35 Max. 85°C VOL (V) 0.30 0.25 Typ. 25°C 0.20 0.15 Min. -40°C 0.10 0.05 0.00 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA) FIGURE 20-25: VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V) 3.5 3.0 Max. -40°C Typ. 25°C 2.5 Min.
PIC16F785/HV785 FIGURE 20-26: VOH vs. IOH OVER TEMPERATURE (VDD = 5.0V) 5.5 5.0 Max. -40°C Typ. 25°C VOH (V) 4.5 Min. 125°C 4.0 3.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 3.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 IOH (mA) FIGURE 20-27: TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE (TTL Input, -40×C TO 125×C) 1.7 1.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) Max.
PIC16F785/HV785 FIGURE 20-28: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE (ST Input, -40×C TO 125×C) 4.0 VIH Max. 125°C Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 3.5 VIH Min. -40°C VIN (V) 3.0 2.5 2.0 VIL Max. -40°C 1.5 VIL Min. 125°C 1.0 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) LFINTOSC FREQUENCY vs. VDD OVER TEMPERATURE (31 kHz) FIGURE 20-29: LFINTOSC 31Khz 45,000 40,000 Max. -40°C 35,000 Typ.
PIC16F785/HV785 FIGURE 20-30: ADC CLOCK PERIOD vs. VDD OVER TEMPERATURE 8 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 125°C 6 Time (μs) 85°C 25°C 4 -40°C 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 20-31: TYPICAL HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE 16 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 14 85°C 12 25°C Time (μs) 10 -40°C 8 6 4 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC16F785/HV785 FIGURE 20-32: MAXIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE -40C to +85C 25 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) Time (μs) 20 15 85°C 25°C 10 -40°C 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 20-33: MINIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE -40C to +85C 10 9 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 8 7 Time (μs) 85°C 6 25°C 5 -40°C 4 3 2 1 0 2.
PIC16F785/HV785 FIGURE 20-34: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (25°C) 5 4 Change from Calibration (%) 3 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 20-35: TYPICAL HFINTOSC FREQUENCY CHANGE OVER DEVICE VDD (85°C) 5 4 Change from Calibration (%) 3 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS41249E-page 180 © 2008 Microchip Technology Inc.
PIC16F785/HV785 FIGURE 20-36: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (125°C) 5 4 Change from Calibration (%) 3 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 20-37: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (-40°C) 5 4 Change from Calibration (%) 3 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2008 Microchip Technology Inc.
PIC16F785/HV785 FIGURE 20-38: TYPICAL VP6 REFERENCE VOLTAGE OVER TEMPERATURE (3V) Typical VP6 Reference Voltage vs. Temperature (VDD=3V) 0.66 0.64 Max. VP6 (V) 0.62 0.6 Typical 0.58 Min. 0.56 0.54 0.52 -40°C 25°C 85°C 125°C Temperature (°C) FIGURE 20-39: TYPICAL VP6 REFERENCE VOLTAGE OVER TEMPERATURE (5V) Typical VP6 Reference Voltage vs. Temperature (VDD=5V) 0.66 0.64 VP6 (V) 0.62 Max. 0.6 Typical 0.58 0.56 Min. 0.54 0.
PIC16F785/HV785 FIGURE 20-40: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, 25°C) Number of Parts 100 80 Parts = 150 60 40 20 1. 23 0 1. 22 4 1. 21 8 1. 21 2 1. 20 6 1. 20 0 1. 19 4 1. 18 8 1. 18 2 1. 17 6 1. 17 0 0 Voltage (V) FIGURE 20-41: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, 85°C) Typical VP6 Reference Voltage Distribution (VDD=3V, 85×C) Number of Parts 70 60 Parts = 150 50 40 30 20 10 1. 23 0 1. 22 4 1. 21 8 1. 21 2 1. 20 6 1. 20 0 1. 19 4 1. 18 8 1. 18 2 1.
PIC16F785/HV785 FIGURE 20-42: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, 125°C) Number of Parts 60 50 Parts = 150 40 30 20 10 1. 23 0 1. 22 4 1. 21 8 1. 21 2 1. 20 6 1. 20 0 1. 19 4 1. 18 8 1. 18 2 1. 17 6 1. 17 0 0 Voltage (V) FIGURE 20-43: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, -40°C) 50 Number of Parts 45 Parts = 150 40 35 30 25 20 15 10 5 1. 23 0 1. 22 4 1. 21 8 1. 21 2 1. 20 6 1. 20 0 1. 19 4 1. 18 8 1. 18 2 1. 17 6 1.
PIC16F785/HV785 FIGURE 20-44: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, 25°C) Typical VP6 Reference Voltage Distribution (VDD=5V, 25×C) 90 Number of Parts 80 Parts = 150 70 60 50 40 30 20 10 30 1. 2 24 1. 2 18 1. 2 12 1. 2 06 1. 2 00 1. 2 94 1. 1 88 1. 1 82 1. 1 76 1. 1 1. 1 70 0 Voltage (V) FIGURE 20-45: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, 85°C) Typical VP6 Reference Voltage Distribution (VDD=5V, 85×C) 70 Number of Parts 60 Parts = 150 50 40 30 20 10 0 1.
PIC16F785/HV785 FIGURE 20-46: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, 125°C) Typical VP6 Reference Voltage Distribution (VDD=5V, 25×C) 40 Number of Parts 35 Parts = 150 30 25 20 15 10 5 1. 23 0 1. 22 4 1. 21 8 1. 21 2 1. 20 6 1. 20 0 1. 19 4 1. 18 8 1. 18 2 1. 17 6 1. 17 0 0 Voltage (V) FIGURE 20-47: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, -40°C) 30 Parts = 150 25 20 15 10 5 6 23 1. 0 23 1. 4 22 1. 8 21 1. 2 21 1. 6 20 1. 0 20 1. 4 19 1. 8 18 1. 2 18 1. 17 1.
PIC16F785/HV785 21.0 PACKAGING INFORMATION 21.1 Package Marking Information The following sections give the technical details of the packages. 20-Lead PDIP Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 20-Lead SOIC (.300”) XXXXXXXXXXXXXX XXXXXXXXXXXXXX XXXXXXXXXXXXXX PIC16F785-I/P 0810017 Example PIC16F785 -E/SO 0810017 YYWWNNN 20-Lead SSOP XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 20-Lead QFN 16F785 -I/ML 0810017 YWWNNN Legend: XX...
PIC16F785/HV785 3 & ' !& " & 4 && 255*** ' '5 # * !( 4 ! ! & 4 % & & # & N E1 NOTE 1 1 2 3 D E A2 A L c A1 b1 eB e b 6 &! ' ! 9 ' &! 7"') % ! 7,8. 7 7 7: ; & 1 , & & < < - < < " # & " # = #& . - - - # # 4 .
PIC16F785/HV785 ! ! " # $%& ! ' 3 & ' !& " & 4 && 255*** ' '5 # * !( 4 ! ! & 4 % & & # & D N E E1 NOTE 1 1 2 3 e b α h h A2 A c φ L A1 6 &! ' ! 9 ' &! 7"') % ! 99 . . 7 7 4 !! & # %% + : = #& # # 4 : ; 1 , 8 & # # 4 7: & : β L1 < < < < < - .
PIC16F785/HV785 () * ! 3 & ' !& " & 4 && 255*** ' '5 &% # * !( 4 ! ! ! & 4 % & & # & D N E E1 NOTE 1 1 2 e b c A2 A φ A1 L1 6 &! ' ! 9 ' &! 7"') % ! 99 . . 7 7 7: ; & : L ? 1 , 8 & < < ? > & # %% < < : . > > # # 4 4 !! = #& # # 4 .
PIC16F785/HV785 + , # * - . /0/0 %1 +, 3 & ' !& " & 4 && 255*** ' '5 # * !( 4 ! ! & 4 % & & # & D D2 EXPOSED PAD e E2 2 E b 2 1 1 K N N NOTE 1 TOP VIEW L BOTTOM VIEW A A1 A3 6 &! ' ! 9 ' &! 7"') % ! 99 . .
PIC16F785/HV785 3 & ' !& " & 4 && 255*** ' '5 DS41249E-page 192 # * !( 4 ! ! & 4 % & & # & © 2008 Microchip Technology Inc.
PIC16F785/HV785 APPENDIX A: DATA SHEET REVISION HISTORY Revision A APPENDIX B: MIGRATING FROM OTHER PIC® DEVICES This is a new data sheet. This discusses some of the issues in migrating from the PIC16F684 PIC® device to the PIC16F785/HV785. Revision B B.1 Updates throughout document. TABLE B-1: Revision C Revised part number to include “HV785”; Added PWM Setup Example; Added Voltage Regulator secton.
PIC16F785/HV785 NOTES: DS41249E-page 194 © 2008 Microchip Technology Inc.
PIC16F785/HV785 INDEX A A/D ...................................................................................... 79 Acquisition Requirements ........................................... 86 Analog Port Pins ......................................................... 80 Associated Registers .................................................. 89 Block Diagram............................................................. 79 Calculating Acquisition Time....................................... 86 Channel Selection...
PIC16F785/HV785 Interrupt Context Saving ........................................... 120 Code Protection ................................................................ 124 Comparator Module ............................................................ 63 Associated Registers .................................................. 74 C1 Output State Versus Input Conditions ................... 63 C2 Output State Versus Input Conditions ................... 66 Comparator Interrupts .................................
PIC16F785/HV785 M MCLR ................................................................................ 110 Internal ...................................................................... 110 .............................................................................................. 9 Data .............................................................................. 9 Data EEPROM Memory............................................ 103 Program ..............................................................
PIC16F785/HV785 PIR1 (Peripheral Interrupt Register 1) ........................ 19 PORTA........................................................................ 35 PORTB........................................................................ 42 PORTC ....................................................................... 45 PWMCLK (PWM Clock Control) ................................. 94 PWMCON0 (PWM Control 0) ..................................... 93 PWMCON1 (PWM Control 1) .................................
PIC16F785/HV785 V Voltage Reference (VR) Specifications............................................................ 157 Voltage Reference Output (VREF) BUFFER Specifications............................................................ 157 Voltage References ............................................................ 70 Associated Registers .................................................. 74 Configuring CVref ....................................................... 70 CVref (Comparator Reference)...........
PIC16F785/HV785 NOTES: DS41249E-page 200 © 2008 Microchip Technology Inc.
PIC16F785/HV785 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC16F785/HV785 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC16F785/HV785 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) Device: PIC16F785(1), PIC16HV785(1), PIC16F785T(2), PIC16HV785T(2); VDD range 4.2V to 5.5V PIC16F785(1), PIC16HV785(1), PIC16F785T(2), PIC16HV785T(2); VDD range 2.0V to 5.
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