Datasheet

PIC16F7X7

DS30498D-page 38  2003-2013 Microchip Technology Inc.

4.6.3 CLOCK TRANSITION AND WDT

When clock switching is performed, the Watchdog

Timer is disabled because the Watchdog Ripple

Counter is used as the Oscillator Start-up Timer (OST).

Once the clock transition is complete (i.e., new oscilla-

tor selection switch has occurred), the Watchdog

Counter is re-enabled with the Counter Reset. This

allows the user to synchronize the Watchdog Timer to

the start of execution at the new clock frequency.

Note: The OST is only used when switching to

XT, HS and LP Oscillator modes.

U-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0

— IRCF2 IRCF1 IRCF0 OSTS

(1)

IOFS SCS1 SCS0

bit 7 bit 0

bit 7 Unimplemented: Read as ‘0’

bit 6-4 IRCF<2:0>: Internal RC Oscillator Frequency Select bits

000 = 31.25 kHz

001 = 125 kHz

010 = 250 kHz

011 = 500 kHz

100 = 1 MHz

101 = 2 MHz

110 = 4 MHz

111 = 8 MHz

bit 3 OSTS: Oscillator Start-up Time-out Status bit

(1)

1 = Device is running from the primary system clock

0 = Device is running from the Timer1 oscillator (T1OSC) or INTRC as a secondary system clock

Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the oscillator

mode.

bit 2 IOFS: INTOSC Frequency Stable bit

1 = Frequency is stable

0 = Frequency is not stable

bit 1-0 SCS<1:0>: Oscillator Mode Select bits

00 = Oscillator mode defined by FOSC<2:0>

01 = T1OSC is used for system clock

10 = Internal RC is used for system clock

11 = Reserved

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown