Datasheet

 2003-2013 Microchip Technology Inc. DS30498D-page 273
PIC16F7X7
Asynchronous Reception with Address Detect......... 143
AUSART Synchronous Receive (Master/Slave) ....... 232
AUSART Synchronous Transmission
(Master/Slave) ..................................................232
Baud Rate Generator with Clock Arbitration............. 120
BRG Reset Due to SDA Arbitration During
Start Condition .................................................. 129
Brown-out Reset .......................................................223
Bus Collision During a Repeated Start
Condition (Case 1)............................................ 130
Bus Collision During a Repeated Start
Condition (Case 2)............................................ 130
Bus Collision During a Stop Condition (Case 1) ....... 131
Bus Collision During a Stop Condition (Case 2) ....... 131
Bus Collision During Start Condition (SCL = 0) ........129
Bus Collision During Start Condition (SDA Only)...... 128
Bus Collision for Transmit and Acknowledge............ 127
Capture/Compare/PWM (CCP1 and CCP2)............. 225
CLKO and I/O ...........................................................222
Clock Synchronization ..............................................113
External Clock...........................................................221
Fail-Safe Clock Monitor............................................. 189
First Start Bit ............................................................. 121
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2
C Bus Data............................................................. 230
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2
C Bus Start/Stop Bits..............................................229
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2
C Master Mode (Reception, 7-bit Address)............ 125
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2
C Master Mode (Transmission, 7 or
10-bit Address) ................................................. 124
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2
C Slave Mode (Transmission, 10-bit Address)....... 111
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2
C Slave Mode (Transmission, 7-bit Address)......... 109
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2
C Slave Mode with SEN = 0 (Reception,
10-bit Address) ................................................. 110
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2
C Slave Mode with SEN = 0 (Reception,
7-bit Address) ...................................................108
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2
C Slave Mode with SEN = 1 (Reception,
10-bit Address) ................................................. 115
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2
C Slave Mode with SEN = 1 (Reception,
7-bit Address) ...................................................114
Low-Voltage Detect................................................... 177
LP Clock to Primary System Clock after
Reset (EC, RC, INTRC)...................................... 46
LP Clock to Primary System Clock after
Reset (HS, XT, LP) .............................................45
Parallel Slave Port ....................................................226
Parallel Slave Port Read.............................................71
Parallel Slave Port Write.............................................71
PWM Output ...............................................................91
Repeated Start Condition..........................................122
Reset, Watchdog Timer, Oscillator Start-up
Timer and Power-up Timer ............................... 223
Slave Mode General Call Address Sequence
(7 or 10-bit Address Mode) ............................... 116
Slave Synchronization (SPI Mode) ............................. 99
Slow Rise Time (MCLR
Tied to VDD
Through RC Network)....................................... 183
SPI Master Mode (CKE = 0, SMP = 0) .....................227
SPI Master Mode (CKE = 1, SMP = 1) .....................227
SPI Mode (Master Mode)............................................ 98
SPI Mode (Slave Mode with CKE = 0)...................... 100
SPI Mode (Slave Mode with CKE = 1)...................... 100
SPI Slave Mode (CKE = 0) ....................................... 228
SPI Slave Mode (CKE = 1) ....................................... 228
Stop Condition Receive or Transmit Mode ...............126
Switching to SEC_RUN Mode .................................... 42
Synchronous Reception (Master Mode, SREN) ....... 147
Synchronous Transmission ...................................... 145
Synchronous Transmission (Through TXEN)........... 145
Time-out Sequence on Power-up (MCLR
Tied to V
DD Through Pull-up Resistor)............. 182
Time-out Sequence on Power-up (MCLR
Tied to V
DD Through RC Network): Case 1...... 182
Time-out Sequence on Power-up (MCLR
Tied to V
DD Through RC Network): Case 2...... 182
Timer0 and Timer1 External Clock ........................... 224
Timer1 Incrementing Edge ......................................... 79
Transition Between SEC_RUN/RC_RUN
and Primary Clock .............................................. 44
Two-Speed Start-up ................................................. 188
Wake-up from Sleep via Interrupt............................. 191
XT, HS, LP, EC, EXTRC to RC_RUN Mode .............. 41
Timing Parameter Symbology .......................................... 220
Timing Requirements
AUSART Synchronous Receive............................... 232
AUSART Synchronous Transmission....................... 232
Capture/Compare/PWM (All CCP Modules)............. 225
CLKO and I/O........................................................... 222
External Clock .......................................................... 221
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2
C Bus Data............................................................. 231
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2
C Bus Start/Stop Bits ............................................. 230
Parallel Slave Port.................................................... 226
Reset, Watchdog Timer, Oscillator Start-up Timer,
Power-up Timer and Brown-out Reset ............. 223
SPI Mode.................................................................. 229
Timer0 and Timer1 External Clock ........................... 224
TMR1CS Bit........................................................................ 78
TMR1ON Bit ....................................................................... 78
TMR2ON Bit ....................................................................... 86
TOUTPS<3:0> Bits ............................................................. 86
TRISA Register................................................................... 49
TRISB Register................................................................... 56
TRISC Register................................................................... 65
TRISD Register................................................................... 67
TRISE Register................................................................... 68
IBF Bit......................................................................... 69
IBOV Bit...................................................................... 69
PSPMODE Bit ...................................................... 67, 68
Two-Speed Clock Start-up Mode...................................... 188
Two-Speed Start-up.......................................................... 169
TXSTA Register
BRGH Bit.................................................................. 133
CSRC Bit .................................................................. 133
TRMT Bit .................................................................. 133
TX9 Bit...................................................................... 133
TX9D Bit ................................................................... 133
TXEN Bit................................................................... 133
V
Voltage Reference Specifications..................................... 218