Datasheet

PIC16F7X7
DS30498D-page 272  2003-2013 Microchip Technology Inc.
PIE1 (Peripheral Interrupt Enable 1)........................... 24
PIE2 (Peripheral Interrupt Enable 2)........................... 26
PIR1 (Peripheral Interrupt Request (Flag) 1) ..............25
PIR2 (Peripheral Interrupt Request (Flag) 2) ..............27
PMCON1 (Program Memory Control 1)...................... 31
RCSTA (Receive Status and Control).......................134
Special Function, Summary..................................18–20
SSPCON (MSSP Control Register 1,
I
2
C Mode)..........................................................104
SSPCON (MSSP Control Register 1,
SPI Mode)...........................................................95
SSPCON2 (MSSP Control Register 2,
I
2
C Mode)..........................................................105
SSPSTAT (MSSP Status, I
2
C Mode)........................103
SSPSTAT (MSSP Status, SPI Mode) .........................94
Status..........................................................................21
T1CON (Timer1 Control).............................................78
T2CON (Timer2 Control).............................................86
TRISE .........................................................................69
TXSTA (Transmit Status and Control) ......................133
WDTCON (Watchdog Timer Control)........................187
Reset......................................................................... 169, 172
Brown-out Reset (BOR). See Brown-out Reset (BOR).
MCLR
Reset. See MCLR.
Power-on Reset (POR). See Power-on Reset (POR).
Reset Conditions for All Registers ....................180, 181
Reset Conditions for PCON Register........................ 179
Reset Conditions for Program Counter.....................179
Reset Conditions for Status Register........................ 179
WDT Reset. See Watchdog Timer (WDT).
Revision History ................................................................265
S
SCI. See AUSART
SCK.....................................................................................93
SDI ......................................................................................93
SDO .................................................................................... 93
Serial Clock, SCK................................................................93
Serial Communication Interface. See AUSART.
Serial Data In, SDI ..............................................................93
Serial Data Out, SDO..........................................................93
Serial Peripheral Interface. See SPI.
Slave Select, SS
.................................................................93
Sleep.................................................................169, 172, 190
Software Simulator (MPLAB SIM).....................................203
Special Features of the CPU.............................................169
Special Function Registers .....................................18, 18–20
SPI Master Mode ................................................................98
SPI Mode ............................................................................ 93
Associated Registers ................................................101
Bus Mode Compatibility ............................................101
Clock...........................................................................98
Effects of a Reset......................................................101
Enabling SPI I/O .........................................................97
Master/Slave Connection............................................ 97
Serial Clock.................................................................93
Serial Data In .............................................................. 93
Serial Data Out ........................................................... 93
Slave Select................................................................93
Slave Select Synchronization .....................................99
Sleep Operation ........................................................101
Typical Connection .....................................................97
SPI Slave Mode ..................................................................99
SS
.......................................................................................93
SSPBUF..............................................................................98
SSPIF Bit.............................................................................25
SSPOV ............................................................................. 123
SSPOV Status Flag .......................................................... 123
SSPSR................................................................................ 98
SSPSTAT Register
R/W
Bit ..................................................................... 107
Stack................................................................................... 29
Overflows.................................................................... 29
Underflows.................................................................. 29
Status Register
C Bit............................................................................ 21
DC Bit ......................................................................... 21
IRP Bit ........................................................................ 21
PD
Bit ................................................................. 21, 172
TO
Bit ................................................................. 21, 172
Z Bit ............................................................................ 21
Synchronous Serial Port Interrupt Flag Bit (SSPIF)............ 25
T
T1CKPS0 Bit....................................................................... 78
T1CKPS1 Bit....................................................................... 78
T1OSCEN Bit...................................................................... 78
T1SYNC
Bit ........................................................................ 78
T2CKPS0 Bit....................................................................... 86
T2CKPS1 Bit....................................................................... 86
T
AD.................................................................................... 157
Timer0................................................................................. 73
Associated Registers.................................................. 76
Clock Source Edge Select (T0SE Bit) ........................ 22
Clock Source Select (T0CS Bit).................................. 22
Interrupt ...................................................................... 73
Operation.................................................................... 73
Overflow Enable (TMR0IE Bit).................................... 23
Overflow Flag (TMR0IF Bit)...................................... 185
Overflow Interrupt ..................................................... 185
Prescaler .................................................................... 74
T0CKI ......................................................................... 74
Use with External Clock.............................................. 74
Timer1................................................................................. 77
Associated Registers.................................................. 83
Asynchronous Counter Mode ..................................... 80
Reading and Writing........................................... 80
Capacitor Selection..................................................... 81
Counter Operation ...................................................... 79
Operation.................................................................... 77
Operation in Synchronized Counter Mode.................. 79
Operation in Timer Mode............................................ 79
Oscillator..................................................................... 81
Oscillator Layout Considerations................................ 81
Prescaler .................................................................... 82
Resetting Timer1 Register Pair................................... 82
Resetting Using a CCP Trigger Output....................... 81
Use as a Real-Time Clock .......................................... 82
Timer2................................................................................. 85
Associated Registers.................................................. 86
Output......................................................................... 85
Postscaler................................................................... 85
Prescaler .................................................................... 85
Prescaler and Postscaler............................................ 85
Timing Diagrams
A/D Conversion......................................................... 234
Acknowledge Sequence ........................................... 126
Asynchronous Master Transmission......................... 139
Asynchronous Master Transmission
(Back to Back) .................................................. 139
Asynchronous Reception.......................................... 140
Asynchronous Reception with Address Byte First.... 143